# US 10,312,239 B2 · Semiconductor memory including semiconductor oxie

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- Number: US 10,312,239 B2
- Document ID: US10312239B2
- Status: Granted
- Kind: B2
- Application number: 15/704,643
- Filed: 2017-09-14
- Published: 2018-09-20
- Granted: 2019-06-04
- Earliest claimed: 2017-03-16
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Tsutomu Tezuka; Fumitaka Arai; Keiji Ikeda; Tomomasa Ueda; Nobuyoshi Saito; Chika Tanaka; Kentaro Miura
- Web page: https://patentgrep.com/patent/US10312239B2

## CPC

- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 12/02: {for one transistor one-capacitor [1T-1C] memory cells}
- H10B 12/50: {Peripheral circuit region structures}
- H10B 41/70: the floating gate being an electrode shared by two or more components
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

## Claims

### Claim 1

A semiconductor memory comprising:
a first interconnect;
a second interconnect;
a member extending in a first direction and including an oxide semiconductor layer, the first direction being parallel to a direction from the first interconnect to the second interconnect, a first end of the oxide semiconductor layer in the first direction electrically connected to the second interconnect, and a second end of the oxide semiconductor layer in the first direction electrically disconnected from the first interconnect, the oxide semiconductor layer including a first portion, second portion and third portion arranged in order from the second end to the first end;
first, second and third conductive layers disposed along the first direction, the first conductive layer facing the first portion, the second conductive layer facing the second portion, and the third conductive layer facing the third portion;
a memory cell provided in a first region including the first portion, the memory cell including a charge storage layer in the first portion;
a first transistor provided in a second region including the second portion; and
a second transistor provided in a third region including the third portion.

### Claim 2 (depends on 1)

The semiconductor memory according to claim 1, wherein
the oxide semiconductor layer extends from the first portion to the second interconnect,
the first transistor includes a first channel region in the second portion, and
the second transistor includes a second channel region in third portion.

### Claim 3 (depends on 1)

The semiconductor memory according to claim 1, wherein
the member includes a semiconductor layer extending in the first direction,
the memory cell includes a third channel region in the semiconductor layer,
a third end of the semiconductor layer in the first direction is electrically connected to the second interconnect; and
a fourth end of the semiconductor layer in the first direction is electrically connected to the first interconnect.

### Claim 4 (depends on 1)

The semiconductor memory according to claim 1, further comprising:
an insulating layer disposed between the first interconnect and the second interconnect and covering the first, second and third conductive layers,
wherein the oxide semiconductor layer is provided between the second interconnect and the insulating layer.

### Claim 5 (depends on 1)

The semiconductor memory according to claim 1, further comprising:
a contact electrically connected to the second interconnect; and
a semiconductor layer provided in the member.

### Claim 6 (depends on 5)

The semiconductor memory according to claim 5, wherein
the second conductive layer is located between the first conductive layer and the third conductive layer,
the contact is located inside the member and extends from the second interconnect to a region between the first conductive layer and the second conductive layer in the first direction, and
the semiconductor layer extends from the first interconnect to the contact.

### Claim 7 (depends on 1)

The semiconductor memory according to claim 1, wherein
a threshold voltage of the memory cell varies in accordance with an amount of charges in the charge storage layer,
the memory cell retains first data where the threshold voltage of the memory cell is a first value, and
the memory cell retains second data different from the first data where the threshold voltage of the memory cell is a second value different from the first value.

### Claim 8 (depends on 7)

The semiconductor memory device according to claim 7, wherein
the charges are supplied from the second interconnect to the oxide semiconductor layer.

### Claim 9 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
another insulating layer provided between the first conductive layer and the first portion, between the second conductive layer and the second portion, and between the third conductive layer and the third portion.