# US 10,312,236 B2 · Techniques providing metal gate devices with multiple barrier layers

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,312,236 B2
- Document ID: US10312236B2
- Status: Granted
- Kind: B2
- Application number: 15/822,360
- Filed: 2017-11-27
- Published: 2018-03-15
- Granted: 2019-06-04
- Earliest claimed: 2011-09-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Xiong-Fei Yu; Chun-Yuan Chou; Kuang-Yuan Hsu; Da-Yuan Lee; Jeff J. Xu
- Web page: https://patentgrep.com/patent/US10312236B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/683: {being parallel to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10P 14/412: {Deposition of metallic or metal-silicide materials}
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P 14/44: Physical vapour deposition [PVD]
- H10W 20/033: {in openings in dielectrics}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

## Claims

### Claim 1

A device comprising:
a first transistor including:
a first high-k (HK) dielectric layer disposed over a semiconductor substrate;
a non-plasma deposited first nitride compound layer formed on top of the first HK dielectric layer such that the non-plasma deposited first nitride compound layer physically contacts the first HK dielectric layer;
a plasma deposited second nitride compound layer formed on top of the non-plasma deposited first nitride compound layer; and
a first metal gate layer disposed over the plasma deposited second nitride compound layer; and
a second transistor including:
a second HK dielectric layer disposed over the semiconductor substrate;
a non-plasma deposited third nitride compound layer formed on top of the second HK dielectric layer such that the non-plasma deposited third nitride compound layer physically contacts the second HK dielectric layer, wherein the non-plasma deposited first nitride compound layer and the non-plasma deposited third nitride compound layer are formed of the same material;
a plasma deposited fourth nitride compound layer formed on top of the non-plasma deposited third nitride compound layer; and
a second metal gate layer disposed over the plasma deposited fourth nitride compound layer, wherein the first metal gate layer is associated with a first type of conductivity and the second metal gate layer is associated with a second type of conductivity that is opposite the first type of conductivity.

### Claim 2 (depends on 1)

The device of claim 1, wherein the non-plasma deposited first nitride compound layer includes a first metal nitride layer having a first ratio of metal to nitrogen and the plasma deposited second nitride compound layer includes a second metal nitride layer having a second ratio of metal to nitrogen, the second ratio being different than the first ratio, and
wherein the non-plasma deposited third nitride compound layer includes a third metal nitride layer having a third ratio of metal to nitrogen and the plasma deposited fourth nitride compound layer includes a fourth metal nitride layer having a fourth ratio of metal to nitrogen, the fourth ratio being different than the third.

### Claim 3 (depends on 1)

The device of claim 1,
wherein the plasma deposited second nitride compound layer and the plasma deposited fourth nitride compound layer are formed of the same type of material.

### Claim 4 (depends on 3)

The device of claim 3, wherein the first metal gate layer comprises an N-type work function layer and the second metal gate layer comprises a P-type work function layer, or the first metal gate layer comprises a P-type work function layer and the second metal gate layer comprises an N-type work function layer.

### Claim 5 (depends on 3)

The device of claim 3, wherein the first metal gate layer physically contacts the plasma deposited second nitride compound layer.

### Claim 6 (depends on 1)

The device of claim 1, wherein the plasma deposited second nitride compound layer has a greater concentration of nitrogen than the non-plasma deposited first nitride compound layer.

### Claim 7 (depends on 1)

The device of claim 1, wherein the non-plasma deposited first nitride compound layer and the non-plasma deposited third nitride compound layer are formed of titanium nitride.

### Claim 8

A device comprising:
a high-k (HK) dielectric layer disposed over a semiconductor substrate;
a first metal compound layer disposed over a first portion and a second portion of the HK dielectric layer, wherein the first metal compound layer includes a non-plasma deposited first nitride compound layer physically contacting the first and second portions HK dielectric layer;
a second metal compound layer disposed over the first metal compound layer that is disposed over the first and second portions of the HK dielectric layer, wherein the second metal compound layer includes a plasma deposited second nitride compound layer disposed above the non-plasma deposited first nitride compound layer;
a first stack of metal gate layers disposed over the first and second metal compound layers disposed over the first portion of the HK dielectric layer, the first stack of metal gate layers including a first work function metal layer; and
a second stack of metal gate layers disposed over the first and second metal compound layers disposed over the second portion of the HK dielectric layer, the second stack of metal gate layers including a second work function metal layer different from the first work function metal layer, wherein the first stack of metal gate layers is associated with a first type of conductivity and the second stack of metal gate layers is associated with a second type of conductivity that is opposite the first type of conductivity.

### Claim 9 (depends on 8)

The device of claim 8, wherein the plasma deposited second nitride compound layer has a greater concentration of nitrogen than the non-plasma deposited first nitride compound layer.

### Claim 10 (depends on 8)

The device of claim 8, wherein the first stack of metal gate layers physically contacts the plasma deposited second nitride compound layer.

### Claim 11 (depends on 8)

The device of claim 8, wherein the first stack of metal gate layers and the second stack of metal gate layers are disposed in an interlayer dielectric layer.

### Claim 12 (depends on 11)

The device of claim 11, wherein the second stack of metal gate layers includes a sidewall spacer that contacts dielectric material of the interlayer dielectric layer.

### Claim 13 (depends on 12)

The device of claim 12, wherein the sidewall spacer contacts an epitaxial growth region disposed in the interlayer dielectric layer.

### Claim 14

A device comprising:
a first gate structure and a second gate structure formed over a semiconductor substrate;
a first sidewall spacer formed along a first sidewall of the first gate structure and a second sidewall spacer along an opposing second sidewall of the first gate structure;
an interlayer dielectric layer formed over the first and second gate structures,
wherein the first gate structure includes:
a first high-k dielectric layer;
a first metal compound layer disposed over the first high-k dielectric layer, the first metal compound layer including a non-plasma deposited first nitride compound layer physically contacting the first high-k dielectric layer;
a second metal compound layer disposed over the first metal compound layer, the second metal compound layer including a plasma deposited second nitride compound layer disposed above the non-plasma deposited first nitride compound layer; and
a first work function metal layer disposed over the second metal compound layer; and
wherein the second gate structure includes:
a second high-k dielectric layer;
a third metal compound layer disposed over the second high-k dielectric layer, the third metal compound layer including a non-plasma deposited third nitride compound layer physically contacting the second high-k dielectric layer, the non-plasma deposited third nitride compound layer and the non-plasma deposited first nitride compound layer being formed of the same material;
a fourth metal compound layer disposed over the third metal compound layer, the fourth metal compound layer including a plasma deposited fourth nitride compound layer disposed above the non-plasma deposited third nitride compound layer; and
a second work function metal layer different from the first work function metal layer disposed over the fourth metal compound layer, wherein a type of conductivity associated with the second work function metal layer is opposite a type of conductivity associated with the first work function metal layer.

### Claim 15 (depends on 14)

The device of claim 14, wherein the first work function metal layer is formed in an N-type transistor.

### Claim 16 (depends on 14)

The device of claim 14, wherein the second work function metal layer is formed in a P-type transistor.

### Claim 17 (depends on 14)

The device of claim 14, wherein the second gate structure includes a third sidewall spacer that contacts dielectric material of the interlayer dielectric layer.

### Claim 18 (depends on 17)

The device of claim 17, further comprising an epitaxial growth region in the interlayer dielectric layer.

### Claim 19 (depends on 18)

The device of claim 18, wherein the third sidewall spacer contacts the epitaxial growth region in the interlayer dielectric layer.

### Claim 20 (depends on 14)

The device of claim 14, wherein the non-plasma deposited first nitride compound layer in titanium nitride.