# US 10,312,233 B2 · Semiconductor device

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- Number: US 10,312,233 B2
- Document ID: US10312233B2
- Status: Granted
- Kind: B2
- Application number: 15/505,508
- Filed: 2015-09-16
- Published: 2017-09-21
- Granted: 2019-06-04
- Earliest claimed: 2014-09-30
- Assignees: Mitsubishi Electric Corporation
- Applicants: Mitsubishi Electric Corporation
- Inventors: Katsutoshi Sugawara; Yasuhiro Kagawa; Rina Tanaka; Yutaka Fukui
- Web page: https://patentgrep.com/patent/US10312233B2

## CPC

- H10D 89/931: {characterised by the dispositions of the protective arrangements}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/378: {Contact regions to the substrate regions}
- H10D 62/8325: {Silicon carbide}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 89/911: {using passive elements as protective elements}
- H10P 30/2042: {into crystalline silicon carbide}
- H10P 30/21: {of electrically active species}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a base region of second conductivity type formed on a drift layer of first conductivity type, a source region of first conductivity type located in the base region, a trench passing through the base region and the source region and dividing cell regions in plan view, a protective diffusion layer of second conductivity type disposed on a bottom of the trench, a gate electrode embedded in the trench with a gate insulating film therebetween, a source electrode electrically connected to the source region, and a protective contact region disposed at each of positions of three or more cell regions and connecting the protective diffusion layer and the source electrode to each other. The protective contact regions are disposed such that a triangle whose vertices are centers of three protective contact regions located closest to one another is an acute triangle.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a drift layer of a first conductivity type provided on said substrate;
a base region of a second conductivity type formed on said drift layer;
a source region of the first conductivity type located in said base region;
a trench passing through said base region and said source region, a bottom of the trench reaching said drift layer, the trench dividing the semiconductor device into a plurality of regions including cell regions and protective contact regions in a plan view;
a protective diffusion layer of the second conductivity type disposed on the bottom of said trench in said drift layer, the protective diffusion layer spanning an entire width of the trench in a cross-sectional view;
a gate insulating film formed on an inner wall of said trench;
a gate electrode embedded in said trench with said gate insulating film therebetween; and
a source electrode electrically connected to said source region,
wherein
three of the protective contact regions closest to one another are disposed at vertices of a triangle in the plan view, the vertices of the triangle corresponding to centers of the three of said-protective contact regions, the triangle being an acute triangle,
each of the protective contact regions connects said protective diffusion layer to said source electrode,
and
said cell regions and said protective contact regions each have a same width in the plan view.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein said trench is formed such that said cell regions are arranged in a lattice pattern.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein said trench is formed such that said cell regions are arranged in a staggered pattern.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein said trench is formed such that said cell regions are arranged in a comb pattern.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein said protective diffusion layer contains an impurity of the second conductivity type within a concentration range of 3×1017 cm−3 or more and 1×1018 cm−3 or less.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein each of said protective contact regions includes a groove having such a depth as to reach said protective diffusion layer.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein
said protective contact regions connect said protective diffusion layer and said source electrode to each other through an ohmic electrode, and
in each of said protective contact regions, said protective diffusion layer includes a high-concentration region having an impurity concentration of the second conductivity type of 5×1018 cm−3 or more and 1×1021 cm−3 or less in an area in contact with said ohmic electrode.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein said substrate comprises a wide-bandgap semiconductor including gallium-nitride-based semiconductor or diamond.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein said substrate comprises silicon carbide.