# US 10,312,232 B1 · Semiconductor devices with package-level configurability

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- Number: US 10,312,232 B1
- Document ID: US10312232B1
- Status: Granted
- Kind: B1
- Application number: 16/007,903
- Filed: 2018-06-13
- Published: 2019-05-16
- Granted: 2019-06-04
- Earliest claimed: 2017-11-13
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: James E. Davis; John B. Pusey; Zhiping Yin; Kevin G. Duesman
- Web page: https://patentgrep.com/patent/US10312232B1

## CPC

- H10D 89/921: {characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses}
- H10D 89/911: {using passive elements as protective elements}
- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10W 90/00: Package configurations
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 1/68: Capacitors having no potential barriers
- H10W 72/01: {Manufacture or treatment}
- H10W 72/07554: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

## Claims

### Claim 1

A semiconductor device assembly, comprising:
a substrate;
a die coupled to the substrate, the die including:
a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and
a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements;
wherein the substrate includes a substrate contact electrically coupled to both the first contact pad and the second contact pad on the die by a single wirebond and a solder ball in electrical contact with the wirebond, the first contact pad and the second contact pad, and
wherein the die further includes a third contact pad electrically coupled to a third circuit on the die including only passive circuit elements, and wherein the substrate contact is electrically coupled to the third contact pad on the die by the wirebond, and wherein the solder ball is further in electrical contact with the third contact pad.

### Claim 2 (depends on 1)

The semiconductor device assembly of claim 1, wherein the die is a first die, further comprising:
a second die including:
a fourth contact pad electrically coupled to a fourth circuit on the second die including at least a second active circuit element, and
a fifth contact pad electrically coupled to a fifth circuit on the second die including only passive circuit elements;
wherein the substrate contact is electrically coupled to the fourth contact pad on the second die, and
wherein the fifth contact pad on the second die is electrically disconnected from the substrate contact.

### Claim 3 (depends on 2)

The semiconductor device assembly of claim 2, wherein the first and second dies are identical dies, wherein the first contact pad on the first die corresponds to the fourth contact pad on the second die, and the second contact pad on the first die corresponds to the fifth contact pad on the second die.

### Claim 4 (depends on 2)

The semiconductor device assembly of claim 2, wherein the first and second dies are stacked in a shingled configuration.

### Claim 5 (depends on 2)

The semiconductor device assembly of claim 2, wherein the substrate contact is electrically coupled to the fourth contact pad by a wirebond between the first and fourth contact pads.

### Claim 6 (depends on 1)

The semiconductor device assembly of claim 1, wherein the first circuit is a driver circuit.

### Claim 7 (depends on 1)

The semiconductor device assembly of claim 1, wherein the second circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.

### Claim 8 (depends on 1)

The semiconductor device assembly of claim 1, wherein the die is a NAND memory die.