# US 10,312,229 B2 · Memory cells including vertical nanowire transistors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,229 B2 - Document ID: US10312229B2 - Status: Granted - Kind: B2 - Application number: 15/789,870 - Filed: 2017-10-20 - Published: 2018-05-03 - Granted: 2019-06-04 - Earliest claimed: 2016-10-28 - Assignees: Synopsys, Inc. - Applicants: Synopsys, Inc. - Inventors: Victor Moroz; Jamil Kawa; Thu Nguyen - Web page: https://patentgrep.com/patent/US10312229B2 ## CPC - H10D 89/10: Integrated device layouts - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - H10B 10/12: {comprising a MOSFET load element} - H10B 10/125: {the MOSFET being a thin film transistor [TFT]} - H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/435: {having multiple laterally adjacent 1D material channels} - H10D 30/6728: {Vertical TFTs} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10D 84/0195: {the components including vertical IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 88/00: Three-dimensional [3D] integrated devices - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A circuit including an SRAM cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. EDA tools for such circuits are also provided. ## Claims ### Claim 1 A circuit, comprising: an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including a first vertical nanowire transistor on top of and connected in series to a second vertical nanowire transistor. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the set consists of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram. ### Claim 4 (depends on 2) The circuit of claim 2, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a rectangle. ### Claim 5 (depends on 2) The circuit of claim 2, wherein the SRAM cell includes: a first intra-cell connector (QR) connecting a current path terminal of the p-type vertical nanowire transistor (PUR) in the fourth column to a current path terminal between the n-type vertical nanowire transistor (PDR) in a first level and the n-type vertical nanowire transistor (PGR) in a second level of the second column, and to gates of the n-type vertical nanowire transistor (PDL) in first level of the first column and of the p-type vertical nanowire transistor (PUL) in the third column; and a second intra-cell connector (QL) connecting a current path terminal of the p-type vertical nanowire transistor (PUL) in the third column to a current path terminal between the n-type vertical nanowire transistor (PDL) in the first level and the n-type vertical nanowire transistor (PGL) in the second level of the first column, and to gates of the n-type vertical nanowire transistor (PDR) in first level of the second column and of the p-type vertical nanowire transistor (PUR) in the fourth column. ### Claim 6 (depends on 5) The circuit of claim 5, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed on opposing sides of the parallelogram. ### Claim 7 (depends on 5) The circuit of claim 5, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed outside of the parallelogram. ### Claim 8 (depends on 5) The circuit of claim 5, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first via being disposed inside of the parallelogram and the second via being disposed outside of the parallelogram. ### Claim 9 (depends on 1) The circuit of claim 1, wherein the SRAM cell includes a first conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a first subset of the vertical nanowire transistor columns, and a second conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a second subset of the vertical nanowire transistor columns. ### Claim 10 (depends on 2) The circuit of claim 2, wherein the SRAM cell includes a first conductor (VSS) disposed beneath and contacting current path terminals of n-type vertical nanowire transistors in the first and second vertical nanowire transistor columns, and a second conductor (VDD) disposed beneath and contacting current path terminals of p-type vertical nanowire transistors in the third and fourth vertical nanowire transistor columns. ### Claim 11 (depends on 2) The circuit of claim 2, where the SRAM cell includes: a first bit line conductor (BL) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the first vertical nanowire transistor column; a second bit line conductor (BL/) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the second vertical nanowire transistor column; and a word line conductor (WL) connected to the gates of the n-type vertical nanowire transistors in the second level of the first and second vertical nanowire transistor columns. ### Claim 12 A computer system adapted to process a computer implemented representation of a circuit design, comprising: a processor and memory coupled to the processor, the memory storing instructions executable by the processor, including instructions to select cells from a cell library and/or to compile a memory layout using a selected cell; the cell library including entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language; and at least one entry in the cell library, or the selected cell, comprising a specification of physical structures and timing parameters of an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including a first vertical nanowire transistor on top of and connected in series to a second vertical nanowire transistor. ### Claim 13 (depends on 12) The computer system of claim 12, wherein the set consists of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. ### Claim 14 (depends on 13) The computer system of claim 13, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram. ### Claim 15 (depends on 13) The computer system of claim 13, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a rectangle. ### Claim 16 (depends on 13) The computer system of claim 13, wherein the SRAM cell includes a first intra-cell connector (QR) connecting a current path terminal of the p-type vertical nanowire transistor (PUR) in the fourth column to a current path terminal between the n-type vertical nanowire transistor (PDR) in a first level and the n-type vertical nanowire transistor (PGR) in a second level of the second column, and to gates of the n-type vertical nanowire transistor (PDL) in first level of the first column and of the p-type vertical nanowire transistor (PUL) in the third column; and a second intra-cell connector (QL) connecting a current path terminal of the p-type vertical nanowire transistor (PUL) in the third column to a current path terminal between the n-type vertical nanowire transistor (PDL) in the first level and the n-type vertical nanowire transistor (PGL) in the second level of the first column, and to gates of the n-type vertical nanowire transistor (PDR) in the first level of the second column and of the p-type vertical nanowire transistor (PUR) in the fourth column. ### Claim 17 (depends on 16) The computer system of claim 16, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed on opposing sides of the parallelogram. ### Claim 18 (depends on 16) The computer system of claim 16, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connectors include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed outside of the parallelogram. ### Claim 19 (depends on 16) The computer system of claim 16, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first via being disposed inside of the parallelogram and the second via being disposed outside of the parallelogram. ### Claim 20 (depends on 12) The computer system of claim 12, wherein the SRAM cell includes a first conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a first subset of the vertical nanowire transistor columns, and a second conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a second subset of the vertical nanowire transistor columns. ### Claim 21 (depends on 13) The computer system of claim 13, wherein the SRAM cell includes a first conductor (VSS) disposed beneath and contacting current path terminals of n-type vertical nanowire transistors in the first and second vertical nanowire transistor columns, and a second conductor (VDD) disposed beneath and contacting current path terminals of p-type vertical nanowire transistors in the third and fourth vertical nanowire transistor columns. ### Claim 22 (depends on 13) The computer system of claim 13, where the SRAM cell includes: a first bit line conductor (BL) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the first vertical nanowire transistor column; a second bit line conductor (BL/) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the second vertical nanowire transistor column; and a word line conductor (WL) connected to the gates of the n-type vertical nanowire transistors in the second level of the first and second vertical nanowire transistor columns. ### Claim 23 (depends on 12) The computer system of claim 12, wherein the instructions further include logic to utilize the specification in said at least one entry to determine a physical placement of the cell. ### Claim 24 A computer program product, comprising: a memory device having stored thereon a machine readable specification of a cell, the specification of the cell including computer readable parameters specifying structural features of a physical implementation of a circuit, the specification being executable by a computer running a placement process to control physical placement of the circuit with other circuits or components or for use by a memory compiler to compile a memory array using the cell, the circuit including: an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including a first vertical nanowire transistor on top of and connected in series to a second vertical nanowire transistor. ### Claim 25 (depends on 24) The computer program product of claim 24, wherein the set consists of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. ### Claim 26 (depends on 25) The computer program product of claim 25, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram. ### Claim 27 (depends on 25) The computer program product of claim 25, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a rectangle. ### Claim 28 (depends on 25) The computer program product of claim 25, wherein the SRAM cell includes: a first intra-cell connector (QR) connecting a current path terminal of the p-type vertical nanowire transistor (PUR) in the fourth column to a current path terminal between the n-type vertical nanowire transistor (PDR) in a first level and the n-type vertical nanowire transistor (PGR) in a second level of the second column, and to gates of the n-type vertical nanowire transistor (PDL) in the first level of the first column and of the p-type vertical nanowire transistor (PUL) in the third column; and a second intra-cell connector (QL) connecting a current path terminal of the p-type vertical nanowire transistor (PUL) in the third column to a current path terminal between the n-type vertical nanowire transistor (PDL) in the first level and the n-type vertical nanowire transistor (PGL) in the second level of the first column, and to gates of the n-type vertical nanowire transistor (PDR) in the first level of the second column and of the p-type vertical nanowire transistor (PUR) in the fourth column. ### Claim 29 (depends on 28) The computer program product of claim 28, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed on opposing sides of the parallelogram. ### Claim 30 (depends on 28) The computer program product of claim 28, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed outside of the parallelogram. ### Claim 31 (depends on 28) The computer program product of claim 28, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first via being disposed inside of the parallelogram and the second via being disposed outside of the parallelogram. ### Claim 32 (depends on 24) The computer program product of claim 24, wherein the SRAM cell includes a first conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a first subset of the vertical nanowire transistor columns, and a second conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a second subset of the vertical nanowire transistor columns. ### Claim 33 (depends on 25) The computer program product of claim 25, wherein the SRAM cell includes a first conductor (VSS) disposed beneath and contacting current path terminals of n-type vertical nanowire transistors in the first and second vertical nanowire transistor columns, and a second conductor (VDD) disposed beneath and contacting current path terminals of p-type vertical nanowire transistors in the third and fourth vertical nanowire transistor columns. ### Claim 34 (depends on 25) The computer program product of claim 25, where the SRAM cell includes: a first bit line conductor (BL) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the first vertical nanowire transistor column; a second bit line conductor (BL/) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the second vertical nanowire transistor column; and a word line conductor (WL) connected to the gates of the n-type vertical nanowire transistors in the second level of the first and second vertical nanowire transistor columns. ### Claim 35 (depends on 24) The computer program product of claim 24, further including logic to utilize the specification of the cell to determine a physical placement of the circuit. ### Claim 36 A circuit, comprising: an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including two vertical nanowire transistors in series, wherein the set consists of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor.