# US 10,312,226 B2 · Semiconductor devices comprising protected side surfaces and related methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,226 B2 - Document ID: US10312226B2 - Status: Granted - Kind: B2 - Application number: 15/728,043 - Filed: 2017-10-09 - Published: 2018-02-01 - Granted: 2019-06-04 - Earliest claimed: 2014-07-08 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Zhaohui Ma; Wei Zhou; Chee Chung So; Soo Loo Ang; Aibin Yu - Web page: https://patentgrep.com/patent/US10312226B2 ## CPC - H10W 90/00: Package configurations - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10P 72/74: {using temporarily an auxiliary support} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 72/0198: {batch processes} - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/014: {using batch processing} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer} - H10W 46/401: {for identification or tracking} - H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates} - H10W 72/07232: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07236: {Soldering or alloying} - H10W 72/07254: {changes in dispositions} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/732: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Methods of protecting semiconductor devices may involve cutting partially through a thickness of a semiconductor wafer to form trenches between stacks of semiconductor dice on regions of integrated circuitry of the semiconductor wafer. A protective material may be dispensed into the trenches and to a level at least substantially the same as a height of the stacks of semiconductor dice. Material of the semiconductor wafer may be removed from a back side thereof at least to a depth sufficient to expose the protective material in the trenches. A remaining thickness of the protective material between the stacks of semiconductor dice may be cut through. ## Claims ### Claim 1 A method, comprising: cutting partially through a thickness of a semiconductor wafer to form trenches of a first width between regions of integrated circuitry of the semiconductor wafer, each region configured to bear a corresponding stack of semiconductor dice thereon each region configured of integrated circuitry configured to operate as logic circuitry; positioning a stack of semiconductor dice comprising memory dice on a surface of each region after forming the trenches, leaving a peripheral portion of the surface of each region exposed; dispensing a protective material only into the trenches, over the exposed peripheral portions of the regions of integrated circuitry, and to a level no higher than a height of the stacks of semiconductor dice to leave bond pads located on the semiconductor die farthest from the semiconductor dice of the stack proximate the semiconductor wafer exposed; removing material of the semiconductor wafer from a back side thereof at least to a depth sufficient to expose the protective material in the trenches at the back side surface of the semiconductor wafer; connecting electrically conductive elements to at least some of the exposed bond pads located on a semiconductor die farthest from a semiconductor die of the stack proximate the semiconductor wafer; and cutting through a remaining thickness of the protective material between the stacks of semiconductor dice and within the trenches by making cuts of a second, narrower width from the semiconductor dice of the stacks farthest from the semiconductor wafer through the protective material to form semiconductor devices having the protective material on sides of the semiconductor dice of the stacks of semiconductor dice and on side surfaces of the regions within the trenches. ### Claim 2 (depends on 1) The method of claim 1, wherein removing the material of the semiconductor wafer from the back side thereof comprises at least one of grinding and abrasively planarizing the back side of the semiconductor wafer to remove the semiconductor material. ### Claim 3 (depends on 1) The method of claim 1, wherein cutting partially through the thickness of the semiconductor wafer comprises cutting partially through the thickness of the semiconductor wafer to a depth greater than a selected final thickness of the semiconductor wafer. ### Claim 4 (depends on 3) The method of claim 3, wherein cutting partially through the thickness of the semiconductor wafer to a depth greater than a selected final thickness of the semiconductor wafer comprises cutting partially through the thickness of the semiconductor wafer to a depth greater than or equal to 40 microns. ### Claim 5 (depends on 1) The method of claim 1, wherein cutting partially through the thickness of the semiconductor wafer comprises cutting partially through the thickness of the semiconductor wafer using a first blade configured to cut through semiconductor material and cutting through the protective material between the stacks of semiconductor dice at least to a level of the exposed protective material comprises cutting through the protective material within the trenches using a second, different blade configured to cut through the protective material. ### Claim 6 (depends on 1) The method of claim 1, wherein cutting partially through the thickness of the semiconductor wafer comprises cutting partially through the thickness of the semiconductor wafer to a width between about one-tenth and about nine-tenths a distance between adjacent regions of the integrated circuitry of the semiconductor wafer. ### Claim 7 (depends on 6) The method of claim 6, wherein forming the trenches to the first width between about one-tenth and about nine-tenths the distance between the adjacent regions of the integrated circuitry of the semiconductor wafer comprises forming the trenches to a width of between about 100 microns and about 200 microns. ### Claim 8 (depends on 1) The method of claim 1, wherein dispensing the protective material in the trenches and to a level no higher than a height of the stacks of semiconductor dice comprises dispensing a flowable dielectric encapsulant material in the trenches and curing the encapsulant material. ### Claim 9 (depends on 1) The method of claim 1, further comprising positioning a protective film over the back side of the semiconductor wafer before cutting completely through the protective material and further comprising cutting through the protective film. ### Claim 10 (depends on 1) The method of claim 1, wherein cutting through the remaining thickness of the protective material between the stacks of semiconductor dice and within the trenches by making the cuts of the second, narrower width from the semiconductor dice of the stacks farthest from the semiconductor wafer through the protective material comprises making the cuts through the protective material without cutting through material of the semiconductor wafer. ### Claim 11 (depends on 1) The method of claim 1, wherein dispensing the protective material into the trenches, over the exposed peripheral portions of the regions of integrated circuitry, and to the level no higher than the height of the stacks of semiconductor dice comprises dispensing the protective material to a level substantially coincident with a height of the stacks of semiconductor dice. ### Claim 12 A method, comprising: cutting partially through a thickness of a semiconductor wafer to form trenches of a first width in streets between regions of integrated circuitry of the semiconductor wafer, the integrated circuitry of each region configured to operate as logic circuitry, each region configured to support a corresponding stack of semiconductor dice thereon; stacking semiconductor dice comprising memory dice on, and operatively connecting the semiconductor dice to, each respective region after forming the trenches, leaving a peripheral portion of each region located laterally between the semiconductor dice and the trenches exposed; placing a protective material only into the trenches, over the exposed peripheral portions of the regions of integrated circuitry, and to a level at least substantially coincident with a maximum height of the semiconductor dice; leaving bond pads located on the semiconductor die farthest from the semiconductor wafer exposed above a maximum height of the protective material; removing semiconductor material of the semiconductor wafer from an inactive surface thereof at least to a depth sufficient to expose the protective material in the trenches at the inactive surface of the semiconductor wafer; connecting electrically conductive elements to at least some of the exposed bond pads located on the semiconductor die farthest from the semiconductor wafer; and cutting through a remaining thickness of the protective material between the semiconductor dice and within the trenches by making cuts of a second, narrower width to form semiconductor devices having the protective material on sides of the semiconductor dice and on side surfaces of the regions of integrated circuitry of the semiconductor wafer within the trenches. ### Claim 13 (depends on 12) The method of claim 12, wherein removing the semiconductor material of the semiconductor wafer from the inactive surface comprises at least one of grinding and abrasively planarizing the inactive surface of the semiconductor wafer to expose the protective material in each trench. ### Claim 14 (depends on 12) The method of claim 12, wherein cutting partially through the thickness of the semiconductor wafer comprises cutting partially through the thickness of the semiconductor wafer to a depth greater than a predetermined final thickness of the semiconductor wafer. ### Claim 15 (depends on 12) The method of claim 12, wherein cutting partially through the thickness of the semiconductor wafer comprises cutting partially through the thickness of the semiconductor wafer using a first blade configured to cut through semiconductor material and wherein cutting through the remaining thickness of the protective material between the semiconductor dice comprises cutting through the protective material using a second, different blade configured to cut through the protective material. ### Claim 16 (depends on 12) The method of claim 12, wherein cutting partially through the thickness of the semiconductor wafer comprises cutting partially through the thickness of the semiconductor wafer to a width between about one-tenth and about nine-tenths a distance between adjacent regions of the integrated circuitry of the semiconductor wafer. ### Claim 17 (depends on 16) The method of claim 16, wherein cutting partially through the thickness of the semiconductor wafer to the width between about one-tenth and about nine-tenths the distance between the adjacent regions of the integrated circuitry of the semiconductor wafer comprises forming the trenches to a width of between about 100 microns and about 200 microns. ### Claim 18 (depends on 12) The method of claim 12, wherein placing the protective material in the trenches and to the level at least substantially coincident with the maximum height of the semiconductor dice comprises dispensing a flowable dielectric encapsulant material in the trenches and curing the encapsulant material. ### Claim 19 (depends on 12) The method of claim 12, further comprising positioning a protective film on the inactive surface of the semiconductor wafer before cutting completely through the protective material and further comprising cutting through the protective film. ### Claim 20 (depends on 12) The method of claim 12, wherein cutting through the remaining thickness of the protective material between the semiconductor dice comprises making the cuts through the protective material without cutting through semiconductor material of the semiconductor wafer.