# US 10,312,222 B2 · Semiconductor package and semiconductor device using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,222 B2 - Document ID: US10312222B2 - Status: Granted - Kind: B2 - Application number: 15/848,083 - Filed: 2017-12-20 - Published: 2018-04-26 - Granted: 2019-06-04 - Earliest claimed: 2015-08-05 - Assignees: Mediatek Inc. - Applicants: MEDIATEK Inc. - Inventors: Wen-Sung Hsu; Shih-Chin Lin; Tao Cheng - Web page: https://patentgrep.com/patent/US10312222B2 ## CPC - H10W 90/00: Package configurations - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 70/657: {on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers} - H10W 72/071: {Connecting or disconnecting} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/721: {of bump connectors} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body. ## Claims ### Claim 1 A semiconductor package, comprising: a substrate; a first electronic component disposed on the substrate; a first conductive layer; a first package body encapsulating the first conductive layer and the first electronic component; and a solder layer connecting the first conductive layer and the substrate; wherein the first conductive layer is embedded in the first package body, and the first conductive layer includes a trace. ### Claim 2 (depends on 1) The semiconductor package as claimed in claim 1, wherein the first conductive layer comprises a first pad exposed from the first package body, and the trace connects with the first pad. ### Claim 3 (depends on 2) The semiconductor package as claimed in claim 2, wherein each of the first pad and the trace has a first lateral surface and a first upper surface, the first upper surface is exposed from the first package body, and the first lateral surface is encapsulated by the first package body. ### Claim 4 (depends on 1) The semiconductor package as claimed in claim 1, wherein the first conductive layer comprises a plurality of the traces formed above the first electronic component. ### Claim 5 (depends on 1) The semiconductor package as claimed in claim 1, wherein the first conductive layer has a thickness ranging between 10 micrometers and 20 micrometers. ### Claim 6 (depends on 1) The semiconductor package as claimed in claim 1, wherein the first package body is a molding compound. ### Claim 7 (depends on 1) The semiconductor package as claimed in claim 1, wherein the first conductive layer has a first upper surface, the first package body has a second upper surface, and the first upper surface is aligned with the second upper surface. ### Claim 8 A semiconductor package, comprising: a substrate; a first electronic component disposed on the substrate; a first conductive layer; a solder layer connecting the first conductive layer and the substrate; a first package body encapsulating the first conductive layer and the first electronic component; a second conductive layer; a second pillar layer connecting the first conductive layer and the second conductive layer; and a second package body encapsulating the second conductive layer and the second pillar layer; wherein the first conductive layer is embedded in the first package body. ### Claim 9 (depends on 8) The semiconductor package as claimed in claim 8, wherein the first conductive layer comprises a first pad exposed from the first package body, and a trace connecting to the first pad. ### Claim 10 (depends on 9) The semiconductor package as claimed in claim 9, wherein each of the first pad and the trace has a first lateral surface and a first upper surface, the first upper surface is exposed from the first package body, and the first lateral surface is encapsulated by the first package body. ### Claim 11 (depends on 8) The semiconductor package as claimed in claim 8, wherein the first conductive layer comprises a plurality of traces formed above the first electronic component, and the second conductive layer comprises a plurality of second pads formed above the traces. ### Claim 12 (depends on 8) The semiconductor package as claimed in claim 8, wherein the first conductive layer has a first upper surface, the first package body has a second upper surface, and the first upper surface is aligned with the second upper surface. ### Claim 13 (depends on 8) The semiconductor package as claimed in claim 8, wherein the second conductive layer comprises a second pad exposed from the second package body. ### Claim 14 (depends on 13) The semiconductor package as claimed in claim 13, wherein the second pad has a second lateral surface and a third upper surface, the third upper surface is exposed from the second package body, and the second lateral surface is encapsulated by the second package body. ### Claim 15 (depends on 8) The semiconductor package as claimed in claim 8, wherein the first conductive layer has a thickness ranging between 10 micrometer and 20 micrometer. ### Claim 16 (depends on 8) The semiconductor package as claimed in claim 8, wherein the first package body is a molding compound. ### Claim 17 (depends on 8) The semiconductor package as claimed in claim 8, wherein the second package body is a lamination layer. ### Claim 18 (depends on 8) The semiconductor package as claimed in claim 8, wherein the second conductive layer has a third upper surface, the second package body has a fourth upper surface, and the third upper surface is aligned with the fourth upper surface. ### Claim 19 (depends on 1) A semiconductor device, comprising: a semiconductor package as claimed in claim 1; and a second electronic component disposed on the first conductive layer of the semiconductor package. ### Claim 20 (depends on 8) A semiconductor device, comprising: a semiconductor package as claimed in claim 8; and a second electronic component disposed on the second conductive layer of the semiconductor package.