# US 10,312,221 B1 · Stacked dies and dummy components for improved thermal performance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,221 B1 - Document ID: US10312221B1 - Status: Granted - Kind: B1 - Application number: 15/844,575 - Filed: 2017-12-17 - Published: 2019-06-20 - Granted: 2019-06-04 - Earliest claimed: 2017-12-17 - Assignees: Advanced Micro Devices, Inc. - Applicants: Rahul Agarwal; Kaushik Mysore Srinivasa Setty; Milind S. Bhagavat; Brett P. Wilkerson - Inventors: Rahul Agarwal; Kaushik Mysore Srinivasa Setty; Milind S. Bhagavat; Brett P. Wilkerson - Web page: https://patentgrep.com/patent/US10312221B1 ## CPC - H10W 90/00: Package configurations - H10W 20/0245: {comprising use of blind vias during the manufacture} - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings} - H10W 72/07231: {Techniques} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/30: Die-attach connectors - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/231: {the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer. The first, second and third insulating bonding layers include a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap. ## Claims ### Claim 1 A semiconductor chip device, comprising: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; a first insulating bonding layer positioned between the first semiconductor chip and the second semiconductor chip and bonding the first semiconductor chip to the second semiconductor chip, the first insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer; plural interconnects between and electrically connecting the first semiconductor chip and the second semiconductor chip; a first dummy component stacked on the first semiconductor chip and separated from the second semiconductor chip by a first gap; a second insulating bonding layer positioned between the first dummy component and the first semiconductor chip and bonding the first dummy component to the first semiconductor chip, the second insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer; and an inorganic insulating layer in the first gap. ### Claim 2 (depends on 1) The semiconductor chip device of claim 1, comprising a second dummy component stacked on the first semiconductor chip and separated from the second semiconductor chip by a second gap, another inorganic insulating layer in the second gap, and a third insulating bonding layer positioned between the second dummy component and the first semiconductor chip and bonding the second dummy component to the first semiconductor chip, the third insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer. ### Claim 3 (depends on 1) The semiconductor chip device of claim 1, comprising wherein the first inorganic insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises silicon oxynitride and the second inorganic insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises SiOx. ### Claim 4 (depends on 1) The semiconductor chip device of claim 1, wherein the inorganic insulating layer and the another inorganic insulating layer comprise a SiOx inner core lined with silicon oxynitride. ### Claim 5 (depends on 1) The semiconductor chip device of claim 1, wherein the interconnects comprise a copper pad metallurgically bonded to a through-chip-via. ### Claim 6 (depends on 2) The semiconductor chip device of claim 2, wherein the first dummy component comprises plural dummy chips stacked together and the second dummy component comprises plural dummy chips stacked together. ### Claim 7 (depends on 2) The semiconductor chip device of claim 2, wherein the first semiconductor chip having a floor plan with a high heat producing area and a low heat producing area, the second semiconductor chip being stacked on the low heat producing area and the first dummy component and the second dummy component being stacked on the high heat producing area. ### Claim 8 (depends on 7) The semiconductor chip device of claim 7, wherein the high heat producing area comprises at least one processor core. ### Claim 9 (depends on 2) The semiconductor chip device of claim 2, wherein the second semiconductor chip comprises a first edge and a second and opposite edge, the first dummy component having an outer edge substantially coterminous with the first edge and the second dummy component having an outer edge substantially coterminous with the second edge. ### Claim 10 A semiconductor chip device, comprising: a stack of plural semiconductor chips, each two adjacent semiconductor chips of the stack of plural semiconductor chips being electrically connected by plural interconnects and physically connected by a first insulating bonding layer, the first insulating bonding layer including a first insulating layer and a second insulating layer bonded to the first insulating layer; a first stack of dummy chips positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap, each two adjacent of the first stack of dummy chips being physically connected by a second insulating bonding layer, the second insulating bonding layer including a first insulating layer and a second insulating layer bonded to the first insulating layer; a second stack of dummy chips positioned opposite a second side of the stack of semiconductor chips and separated from the stack of plural semiconductor chips by a second gap, each two adjacent of the second stack of dummy chips being physically connected by a third insulating bonding layer, the third insulating bonding layer including a first insulating layer and a second insulating layer bonded to the first insulating layer; and an insulating layer in the first gap and another insulating layer in the second gap. ### Claim 11 (depends on 10) The semiconductor chip device of claim 10, comprising another semiconductor chip, the stack of semiconductor chips being positioned on the another semiconductor chip. ### Claim 12 (depends on 11) The semiconductor chip device of claim 11, wherein the another semiconductor chip having a floor plan with a high heat producing area and a low heat producing area, the stack of semiconductor chips being stacked on the low heat producing area and the first stack of dummy chips and the second stack of dummy chips being stacked on the high heat producing area. ### Claim 13 (depends on 11) The semiconductor chip device of claim 11, wherein the second semiconductor chip comprises a first edge and a second and opposite edge, the first dummy component having an outer edge substantially coterminous with the first edge and the second dummy component having an outer edge substantially coterminous with the second edge. ### Claim 14 (depends on 10) The semiconductor chip device of claim 10, comprising wherein the first insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises silicon oxynitride and the second insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises SiOx. ### Claim 15 (depends on 10) The semiconductor chip device of claim 10, wherein the insulating layer and the another insulating layer comprise a SiOx inner core lined with silicon oxynitride. ### Claim 16 (depends on 10) The semiconductor chip device of claim 10, wherein the interconnects comprise a copper pad metallurgically bonded to a through-chip-via. ### Claim 17 A method of manufacturing, comprising: stacking a second semiconductor chip on a first semiconductor chip; forming a first insulating bonding layer between the first semiconductor chip and the second semiconductor chip bonding the first semiconductor chip to the second semiconductor chip, the first insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer; forming plural interconnects between and electrically connecting the first semiconductor chip and the second semiconductor chip; stacking a first dummy component on the first semiconductor chip and separated from the second semiconductor chip by a first gap; forming a second insulating bonding layer between the first dummy component and the first semiconductor chip and bonding the first dummy component to the first semiconductor chip, the second insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer; and forming an inorganic insulating layer in the first gap. ### Claim 18 (depends on 17) The method of claim 17, comprising stacking a second dummy component on the first semiconductor chip and separated from the second semiconductor chip by a second gap and, forming a third insulating bonding layer between the second dummy component and the first semiconductor chip and bonding the second dummy component to the first semiconductor chip, the third insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer, and forming another inorganic insulating layer in the second gap. ### Claim 19 (depends on 17) The method of claim 17, wherein the first inorganic insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises silicon oxynitride and the second inorganic insulating layer of the of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises SiOx. ### Claim 20 (depends on 17) The method of claim 17, wherein the inorganic insulating layer and the another inorganic insulating layer comprise a SiOx inner core lined with silicon oxynitride. ### Claim 21 (depends on 18) The method of claim 18, wherein the first dummy component comprises plural dummy chips stacked together and the second dummy component comprises plural dummy chips stacked together. ### Claim 22 (depends on 18) The method of claim 18, wherein the second semiconductor chip comprises a first edge and a second and opposite edge, the first dummy component having an outer edge substantially coterminous with the first edge and the second dummy component having an outer edge substantially coterminous with the second edge.