# US 10,312,220 B2 · Semiconductor package and fabricating method thereof

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- Number: US 10,312,220 B2
- Document ID: US10312220B2
- Status: Granted
- Kind: B2
- Application number: 15/707,646
- Filed: 2017-09-18
- Published: 2018-01-04
- Granted: 2019-06-04
- Earliest claimed: 2016-01-27
- Assignees: Amkor Technology, Inc.
- Applicants: Amkor Technology, Inc.
- Inventors: David Hiner; Michael Kelly; Ronald Huemoeller
- Web page: https://patentgrep.com/patent/US10312220B2

## CPC

- H10W 90/00: Package configurations
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.

## Claims

### Claim 1

A method of making an electronic device, the method comprising:
receiving a first portion of a signal redistribution (RD) structure;
forming a first RD interconnection structure on the signal redistribution structure;
forming a second RD interconnection structure on the signal redistribution structure;
coupling a back side of a connect die to the signal redistribution structure, the connect die comprising a first connect die interconnection structure coupled to a front side of the connect die and a second connect die interconnection structure coupled to the front side of the connect die;
coupling a first interconnection structure of a first functional die to the first RD interconnection structure; and
coupling a second interconnection structure of the first functional die to the first connect die interconnection structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
said receiving the first portion of the signal redistribution structure comprises receiving the first portion of the signal distribution structure on a carrier; and
the method further comprises removing the carrier.

### Claim 3 (depends on 1)

The method of claim 1, comprising:
coupling a third interconnection structure of a second functional die to the second RD interconnection structure; and
coupling a fourth interconnection structure of the second functional die to the second connect die interconnection structure.

### Claim 4 (depends on 2)

The method of claim 2, comprising after said removing the carrier, adding at least one dielectric layer and at least one conductive layer to the signal redistribution structure.

### Claim 5 (depends on 1)

The method of claim 1, comprising before said coupling the first and second interconnection structures of the first functional die, encapsulating the first RD interconnection structure and the first connect die interconnection structure in a first encapsulating material.

### Claim 6 (depends on 5)

The method of claim 5, wherein said encapsulating comprises thinning the encapsulating material.

### Claim 7 (depends on 5)

The method of claim 5, comprising underfilling between the first functional die and the encapsulating material.

### Claim 8 (depends on 5)

The method of claim 5, comprising forming a second encapsulating material on the first encapsulating material and covering at least lateral sides of the first functional die.

### Claim 9

A method of making an electronic device, the method comprising:
providing a first functional die, wherein the first functional die comprises:
first die interconnection structures on a front side of the first functional die, the first die interconnection structures having a first pitch; and
second die interconnection structures on the front side of the first functional die, the second die interconnection structures having a second pitch greater than the first pitch;
encapsulating the first functional die in an encapsulating material, wherein the encapsulating material covers at least a sidewall of the first functional die and does not cover the front side of the first functional die; and
after said encapsulating:
coupling a connect die to the first functional die by, at least in part, attaching first connect die interconnection structures on a front side of the connect die to the first die interconnection structures of the first functional die; and
coupling the second die interconnection structures of the first functional die to a substrate.

### Claim 10 (depends on 9)

The method of claim 9, wherein:
said providing the first functional die comprises coupling the front side of the first functional die to a carrier;
said encapsulating comprises encapsulating the first functional die coupled to the carrier; and
the method further comprises removing the carrier.

### Claim 11 (depends on 10)

The method of claim 10, wherein said coupling the front side of the first functional die to the carrier comprises inserting the first and second die interconnection structures of the first functional die into an adhesive layer.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
coupling a front side of a second functional die to the carrier, the front side of the second functional die comprising third die interconnection structures having a third height and third pitch, and fourth die interconnection structures having a fourth height, greater than the third height, and a fourth pitch, greater than the third pitch;
coupling the connect die to the second functional die by, at least in part, attaching second connect die interconnection structures on the front side of the connect die to the third die interconnection structures of the second functional die; and
coupling the fourth die interconnection structures of the second functional die to the substrate.

### Claim 13 (depends on 9)

The method of claim 9, wherein:
the first die interconnection structures have a first height; and
the second die interconnection structures have a second height greater than the first height.

### Claim 14 (depends on 9)

The method of claim 9, comprising forming an underfill between the connect die and the first functional die.

### Claim 15 (depends on 9)

The method of claim 9, comprising forming an underfill between a back side of the connect die and the substrate.

### Claim 16 (depends on 9)

The method of claim 9, wherein a bottom side of the encapsulating material and the front side of the first functional die are coplanar.

### Claim 17 (depends on 9)

The method of claim 9, wherein a top side of the encapsulating material and a back side of the first functional die are coplanar.

### Claim 18

A method of making an electronic device, the method comprising:
coupling a front side of a first functional die to a carrier;
encapsulating the first functional die coupled to the carrier in an encapsulating material; and
after said encapsulating:
removing the carrier;
forming first die interconnection structures on the front side of the first functional die, the first die interconnection structures having a first height and a first pitch;
forming second die interconnection structures on the front side of the first functional die, the second die interconnection structures having a second height, greater than the first height, and a second pitch, greater than the first pitch;
coupling a connect die to the first functional die by, at least in part, connecting first connect die interconnection structures on a front side of the connect die to the first die interconnection structures of the first functional die; and
coupling the second die interconnection structures of the first functional die to a substrate.

### Claim 19 (depends on 18)

The method of claim 18, comprising:
coupling a front side of a second functional die to the carrier;
forming third die interconnection structures on the front side of the second functional die, the third die interconnection structures having a third height and a third pitch;
forming fourth die interconnection structures on the front side of the second functional die, the fourth die interconnection structures having a fourth height, greater than the third height, and a fourth pitch, greater than the third pitch;
coupling the connect die to the second functional die by, at least in part, attaching second connect die interconnection structures on the front side of the connect die to the third die interconnection structures of the second functional die; and
coupling the fourth die interconnection structures of the second functional die to the substrate.

### Claim 20 (depends on 18)

The method of claim 18, comprising forming an underfill between the connect die and the functional die.

### Claim 21 (depends on 18)

The method of claim 18, comprising forming an underfill between a back side of the connect die and the substrate.

### Claim 22 (depends on 18)

The method of claim 18, wherein a bottom side of the encapsulating material and the front side of the first functional die are coplanar.

### Claim 23 (depends on 18)

The method of claim 18, wherein a top side of the encapsulating material and a back side of the first functional die are coplanar.