# US 10,312,219 B2 · Semiconductor device assemblies including multiple shingled stacks of semiconductor dies

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- Number: US 10,312,219 B2
- Document ID: US10312219B2
- Status: Granted
- Kind: B2
- Application number: 15/806,808
- Filed: 2017-11-08
- Published: 2019-05-09
- Granted: 2019-06-04
- Earliest claimed: 2017-11-08
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hong Wan Ng; Akshay N. Singh
- Web page: https://patentgrep.com/patent/US10312219B2

## CPC

- H10W 90/00: Package configurations
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/075: {of bond wires}
- H10W 72/07554: {changes in dispositions}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/231: {the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor device assembly includes a substrate having a plurality of external connections, a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack.

## Claims

### Claim 1

A semiconductor device assembly, comprising:
a substrate including a plurality of external connections;
a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections;
a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections; and
an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack,
wherein the first shingled stack of semiconductor dies comprise memory dies corresponding to a first memory channel of the semiconductor device assembly, and
wherein the second shingled stack of semiconductor dies comprise memory dies corresponding to a second memory channel of the semiconductor device assembly.

### Claim 2 (depends on 1)

The semiconductor device assembly of claim 1, wherein:
the first shingled stack of semiconductor dies are electrically connected to the first subset of the plurality of external connections by a first plurality of wirebonds, and
the second shingled stack of semiconductor dies are electrically connected to the second subset of the plurality of external connections by a second plurality of wirebonds.

### Claim 3 (depends on 1)

The semiconductor device assembly of claim 1, wherein:
the substrate includes a first plurality of bondfingers corresponding to the first shingled stack and a second plurality of bondfingers corresponding to the second shingled stack,
each of the first plurality of bondfingers is directly coupled to only one of the first plurality of wirebonds, and
each of the second plurality of bondfingers is directly coupled to only one of the second plurality of wirebonds.

### Claim 4 (depends on 1)

The semiconductor device assembly of claim 1, wherein the first shingled stack and the second shingled stack include a same number of semiconductor dies.

### Claim 5 (depends on 4)

The semiconductor device assembly of claim 4, wherein the numbers is one of two, four, eight, or sixteen.

### Claim 6 (depends on 1)

The semiconductor device assembly of claim 1, wherein:
the first shingled stack includes a lowermost semiconductor die of the first shingled stack and at least one upper semiconductor die stacked over the lowermost semiconductor die of the first shingled stack, and
each upper semiconductor die of the first shingled stack is offset from a semiconductor die directly below by a first offset in a first direction.

### Claim 7 (depends on 6)

The semiconductor device assembly of claim 6, wherein:
the second shingled stack includes a lowermost semiconductor die of the second shingled stack and at least one upper semiconductor die stacked over the lowermost semiconductor die of the second shingled stack, and
each upper semiconductor die of the second shingled stack is offset from a semiconductor die directly below by a second offset in a second direction.

### Claim 8 (depends on 7)

The semiconductor device assembly of claim 7, wherein the first offset is substantially equal to the second offset.

### Claim 9 (depends on 7)

The semiconductor device assembly of claim 7, wherein the first direction is substantially equal to the second direction.

### Claim 10 (depends on 7)

The semiconductor device assembly of claim 7, wherein the first direction is substantially opposite to the second direction.

### Claim 11 (depends on 7)

The semiconductor device assembly of claim 7, wherein the first direction is substantially orthogonal to the second direction.

### Claim 12 (depends on 1)

The semiconductor device assembly of claim 1, further comprising at least one I/O expander electrically coupled to a third subset of the plurality of external connections.

### Claim 13 (depends on 1)

The semiconductor device assembly of claim 1, further comprising:
a third shingled stack of semiconductor dies disposed directly over a third location on the substrate and electrically coupled to a third subset of the plurality of external connections; and
a fourth shingled stack of semiconductor dies disposed directly over a fourth location on the substrate and electrically coupled to a fourth subset of the plurality of external connections.

### Claim 14 (depends on 13)

The semiconductor device assembly of claim 13, wherein:
the third shingled stack of semiconductor dies comprise memory dies corresponding to a third memory channel, and
the fourth shingled stack of semiconductor dies comprise memory dies corresponding to a fourth memory channel.