# US 10,312,216 B2 · Systems and methods for bonding semiconductor elements

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- Number: US 10,312,216 B2
- Document ID: US10312216B2
- Status: Granted
- Kind: B2
- Application number: 15/905,408
- Filed: 2018-02-26
- Published: 2018-06-28
- Granted: 2019-06-04
- Earliest claimed: 2013-10-08
- Assignees: Kulicke and Soffa Industries, Inc.
- Applicants: Kulicke and Soffa Industries, Inc.
- Inventors: Robert N. Chylak; Dominick A. DeAngelis
- Web page: https://patentgrep.com/patent/US10312216B2

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/07141: {Means for applying energy, e.g. ovens or lasers}
- H10W 72/07178: {Means for aligning}
- H10W 72/07183: {Means for monitoring}
- H10W 72/072: {of bump connectors}
- H10W 72/07221: {Aligning}
- H10W 72/07223: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07231: {Techniques}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07233: {Ultrasonic bonding, e.g. thermosonic bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 80/314: {characterized by direct bonding of pads or other interconnections}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures.

## Claims

### Claim 1

A method of ultrasonically bonding semiconductor elements, the method comprising the steps of:
(a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; and
(b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures.

### Claim 2 (depends on 1)

The method of claim 1 wherein the first semiconductor element is a semiconductor die.

### Claim 3 (depends on 1)

The method of claim 1 wherein each of the first semiconductor element and the second semiconductor element is a respective semiconductor die.

### Claim 4 (depends on 1)

The method of claim 1 wherein the first semiconductor element includes a semiconductor die.

### Claim 5 (depends on 1)

The method of claim 1 wherein each of the first semiconductor element and the second semiconductor element includes a respective semiconductor die.

### Claim 6 (depends on 1)

The method of claim 1 further comprising the step of moving the first semiconductor element towards the second semiconductor element such that lower surfaces of the first conductive structures contact upper surfaces of the respective second conductive structures.

### Claim 7 (depends on 1)

The method of claim 1 further comprising the step of applying pressure between the first semiconductor element and the second semiconductor element during at least a portion of step (b).

### Claim 8 (depends on 1)

The method of claim 1 further comprising the step of deforming ones of the first conductive structures during step (b).

### Claim 9 (depends on 1)

The method of claim 1 wherein step (b) is conducted at ambient temperature.

### Claim 10 (depends on 1)

The method of claim 1 further comprising the step of heating at least one of the first semiconductor element and the second semiconductor element during at least a portion of step (b).

### Claim 11 (depends on 1)

The method of claim 1 further comprising the step of heating the first semiconductor element, during at least a portion of step (b), using a bonding tool that retains the first semiconductor element.

### Claim 12 (depends on 1)

The method of claim 1 further comprising the step of heating the second semiconductor element, during at least a portion of step (b), using a support structure that supports the second semiconductor element during step (b).

### Claim 13 (depends on 1)

The method of claim 1 wherein at least one of the plurality of first conductive structures and the plurality of second conductive structures includes a plurality of copper pillar structures.

### Claim 14 (depends on 1)

The method of claim 1 wherein step (b) includes ultrasonically bonding the ones of the first conductive structures to the respective ones of the second conductive structures using a bonding tool that retains the first semiconductor element during step (b).

### Claim 15 (depends on 14)

The method of claim 14 wherein the bonding tool is engaged with an ultrasonic transducer for providing ultrasonic energy during step (b).

### Claim 16 (depends on 14)

The method of claim 14 wherein the bonding tool retains the first semiconductor element during step (b) using vacuum.

### Claim 17 (depends on 1)

The method of claim 1 wherein the ultrasonic bonding of step (b) results in a package on package structure with regard to the first semiconductor element and the second semiconductor element.

### Claim 18 (depends on 1)

The method of claim 1 wherein steps (a) and (b) are performed on a thermos-compression bonding machine.

### Claim 19 (depends on 1)

The method of claim 1 wherein the second semiconductor element is a processor and the first semiconductor element is a memory device.

### Claim 20 (depends on 1)

The method of claim 1 wherein the second semiconductor element is an application processor unit and the first semiconductor element is a memory device.