# US 10,312,212 B2 · Self-adhesive die

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- Number: US 10,312,212 B2
- Document ID: US10312212B2
- Status: Granted
- Kind: B2
- Application number: 14/541,208
- Filed: 2014-11-14
- Published: 2015-06-18
- Granted: 2019-06-04
- Earliest claimed: 2013-09-23
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Rongwei Zhang
- Web page: https://patentgrep.com/patent/US10312212B2

## CPC

- H10W 72/00: Interconnections or connectors in packages
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 62/117: {Shapes of semiconductor bodies}
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/417: {Bonding materials between chips and die pads}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10W 72/01323: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/0198: {batch processes}
- H10W 72/07331: {Connecting techniques}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/931: {Shapes of bond pads}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An apparatus for enhancing the thermal performance of semiconductor packages effectively. The concept of this invention is to provide silicon nanowires on the backside of an integrated circuit die to directly attach the die to the substrate, thereby improving the interface between die and substrate, and thus enhancing thermal performance and enhancing reliability by improving adhesion.

## Claims

### Claim 1

A semiconductor package comprising:
a semiconductor die, including an active side and an opposite back side, the opposite back side shaped as a plurality of nanowires, a plurality of cavities between the plurality of nanowires; and
a substrate having a first side, the opposite back side of the semiconductor die attached to the first side of the substrate.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the plurality of nanowires are of silicon.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the semiconductor die is pressure fit to the first side of the substrate via the plurality of nanowires.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein each of the plurality of nanowires is between 10 nanometers and 1 micrometer in diameter.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein each of the plurality of nanowires is less than 20 micrometer in length.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the substrate is a laminate.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein the plurality of nanowires includes one of an amine based, a sulfur based, and a phosphorous based silane coupling agents.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the substrate is a leadframe.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, wherein the leadframe includes a die attach pad, the opposite back side of the semiconductor die being attached to the die attach pad.

### Claim 10 (depends on 8)

The semiconductor package of claim 8, wherein the leadframe includes a roughened surface that is in contact with the plurality of nanowires.

### Claim 11 (depends on 1)

The semiconductor package of claim 1, wherein the opposite back side of the semiconductor die is shaped as a plurality of nanowires by metal assisted chemical etching.

### Claim 12

A semiconductor package comprising:
a semiconductor die, including an active side and an opposite back side, the opposite back side shaped as a plurality of nanowires, the opposite back side including a plurality of cavities in between the plurality of nanowires;
a substrate having a first side, the opposite back side of the semiconductor die attached to the first side of the substrate; and
mold compound in the plurality of cavities.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein each of the plurality of cavities is less than 20 μm deep.

### Claim 14 (depends on 12)

The semiconductor package of claim 12, wherein the plurality of nanowires includes one of an amine based, a sulfur based, and a phosphorous based silane coupling agents.

### Claim 15 (depends on 12)

The semiconductor package of claim 12, wherein the substrate is a leadframe.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein the leadframe includes a die attach pad, the opposite back side of the semiconductor die being attached to the die attach pad.

### Claim 17 (depends on 12)

The semiconductor package of claim 12, wherein the substrate is a laminate.

### Claim 18 (depends on 12)

The semiconductor package of claim 12, wherein the plurality of nanowires and the plurality of cavities together cover an entire area of the opposite back side.