# US 10,312,210 B2 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,210 B2 - Document ID: US10312210B2 - Status: Granted - Kind: B2 - Application number: 15/949,868 - Filed: 2018-04-10 - Published: 2018-08-16 - Granted: 2019-06-04 - Earliest claimed: 2014-11-07 - Assignees: Mediatek Inc. - Applicants: MediaTek Inc. - Inventors: Ching-Liou Huang; Ta-Jen Yu - Web page: https://patentgrep.com/patent/US10312210B2 ## CPC - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/635: {Through-vias} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing} - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/01255: {by using masks} - H10W 72/019: {of bond pads} - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/01938: {in gaseous form, e.g. by CVD or PVD} - H10W 72/01953: {by etching} - H10W 72/072: {of bump connectors} - H10W 72/07254: {changes in dispositions} - H10W 72/073: {of die-attach connectors} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/354: {comprising polymers} - H10W 72/387: {Flow barriers} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/147: {the encapsulations being multilayered} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/731: {of die-attach connectors} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via. ## Claims ### Claim 1 A semiconductor package, comprising: a base having a device-attach surface; a first conductive via and a second conductive via passing through the base; a semiconductor die mounted on the base by a first conductive structure and a second conductive structure, wherein the first conductive structure is in direct physical contact and partially overlaps with a first terminal surface of the first conductive via, and the second conductive structure is in direct contact and fully overlaps with a second terminal surface of the second conductive via. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein: a first interface between the first conductive structure and the first terminal surface has a smaller area in plan view than the first terminal surface. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein: the device-attach surface comprises a base material, and wherein the first conductive structure is in direct contact with the base material in the device-attach surface. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein: the second conductive structure is not in contact with the base material in the device-attach surface. ### Claim 5 (depends on 1) The semiconductor package of claim 1, further comprising: an underfill material covering the first and second conductive vias and in direct contact with the device-attach surface. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the first conductive structure comprises a conductive pillar and a conductive solder cap, and the conductive solder cap is in direct contact and partially overlaps with the first terminal surface of the first conductive via. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the first conductive structure is coupled to a power pad or ground pad of the semiconductor die. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the first conductive structure is a bump on trace structure and rectangular in a plan view. ### Claim 9 A semiconductor package, comprising: a base having a device-attach surface comprising a base material; a first conductive via and a second conductive via passing through the base; a first conductive structure in direct physical contact with a first terminal surface of the first conductive via and the base material in the device-attach surface, forming a first interface between the first conductive structure and the first terminal surface, wherein the first conductive structure partially overlaps with the first conductive via such that, in plan view, the first interface has a smaller area than the first terminal surface; and a second conductive structure is in direct contact and fully overlaps with the second conductive via. ### Claim 10 (depends on 9) The semiconductor package of claim 9, further comprising: a semiconductor die mounted on the base by the first conductive structure, and wherein the base has a solder-ball attach surface opposite to the device-attach surface, wherein the solder-ball attach surface is away from the semiconductor die. ### Claim 11 (depends on 10) The semiconductor package of claim 10, further comprising: a solder-ball disposed on the solder-ball attach surface of the base and in contact with the first conductive via, wherein a second interface between the first conductive via and the solder-ball is opposite to the first interface. ### Claim 12 (depends on 11) The semiconductor package of claim 11, wherein the first interface is aligned to the device-attach surface of the base, and the second interface is not coplanar with the solder-ball attach surface of the base. ### Claim 13 (depends on 11) The semiconductor package of claim 11, wherein the solder-ball fully overlaps with the first conductive structure in plan view. ### Claim 14 (depends on 11) The semiconductor package of claim 11, wherein the solder-ball partially overlaps with the first conductive structure in plan view.