# US 10,312,209 B2 · Manufacturing method of semiconductor package

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- Number: US 10,312,209 B2
- Document ID: US10312209B2
- Status: Granted
- Kind: B2
- Application number: 15/951,930
- Filed: 2018-04-12
- Published: 2018-08-16
- Granted: 2019-06-04
- Earliest claimed: 2013-11-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Chao-Wen Shih; Kai-Chiang Wu; Ching-Feng Yang; Ming-Kai Liu; Shih-Wei Liang; Yen-Ping Wang
- Web page: https://patentgrep.com/patent/US10312209B2

## CPC

- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10W 74/01: Manufacture or treatment
- H10W 74/016: {using moulds}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01257: {by reflowing}
- H10W 72/019: {of bond pads}
- H10W 72/072: {of bump connectors}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/287: {Flow barriers}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/987: {Flow barriers}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

## Claims

### Claim 1

A method of manufacturing a semiconductor package, comprising:
patterning a first region and a second region on a post-passivation interconnect (PPI), the second region being an oxide or a nitride derivative of the first region; and
annealing the first region and the second region on the PPI with a first temperature heat treatment;
wherein the first region is surrounded by the second region.

### Claim 2 (depends on 1)

The method of manufacturing a semiconductor package in claim 1, wherein the patterning the first region and the second region on the PPI further comprises forming a mask layer over the PPI.

### Claim 3 (depends on 2)

The method of manufacturing a semiconductor package in claim 2, wherein the forming the mask layer over the PPI comprises forming a mask layer in contact with the PPI.

### Claim 4 (depends on 2)

The method of manufacturing a semiconductor package in claim 2, wherein the forming the mask layer over the PPI comprises positioning a first stencil plate over the PPI.

### Claim 5 (depends on 4)

The method of manufacturing a semiconductor package in claim 4, further comprising forming a flux layer in the first region of the PPI by positioning a second stencil plate over the PPI.

### Claim 6 (depends on 5)

The method of manufacturing a semiconductor package in claim 5, further comprising:
dropping a solder ball on the flux layer; and
reflowing the solder ball to form a solder bump.

### Claim 7 (depends on 6)

The method of manufacturing a semiconductor package in claim 6, further comprising forming an electrical connection between an external device and the solder bump.

### Claim 8 (depends on 1)

The method of manufacturing a semiconductor package in claim 1, wherein the patterning the first region and the second region of the PPI comprises an oxygen plasma surface treatment.

### Claim 9

A method of manufacturing a semiconductor package, comprising:
patterning a metal derivative in a second region of a post-passivation interconnect (PPI) by covering a first region of the PPI with a photoresist;
dropping a solder ball on the first region; and
forming an electrical connection between the solder ball and the PPI.

### Claim 10 (depends on 9)

The method of manufacturing a semiconductor package in claim 9, wherein the first region is surrounded by the second region.

### Claim 11 (depends on 9)

The method of manufacturing a semiconductor package in claim 9, wherein the patterning the metal derivative comprises applying a stencil plate over but free of contact with the PPI.

### Claim 12 (depends on 9)

The method of manufacturing a semiconductor package in claim 9, further comprising forming a flux layer on the first region of the PPI.

### Claim 13 (depends on 12)

The method of manufacturing a semiconductor package in claim 12, wherein the forming the flux layer comprises a screen printing operation or a photolithography operation.

### Claim 14 (depends on 12)

The method of manufacturing a semiconductor package in claim 12, wherein a width of the flux layer as formed is narrower than a width of the first region.

### Claim 15

A method of manufacturing a semiconductor package, comprising:
patterning a metal derivative having a thickness of from about 1 μm to about 3 μm in a second region of a post-passivation interconnect (PPI), the metal derivative comprising metal oxide or metal nitride; and
disposing a solder ball on a first region of the PPI, wherein the first region is surrounded by the second region.

### Claim 16 (depends on 15)

The method of manufacturing a semiconductor package in claim 15, further comprising annealing the PPI with a first temperature heat treatment from about 100 to about 250 degrees Celsius.

### Claim 17 (depends on 16)

The method of manufacturing a semiconductor package in claim 16, wherein the patterning the metal derivative comprises applying an oxygen plasma surface treatment.

### Claim 18 (depends on 17)

The method of manufacturing a semiconductor package in claim 17, wherein the annealing the PPI is performed concurrently with applying the oxygen plasma surface treatment.

### Claim 19 (depends on 15)

The method of manufacturing a semiconductor package in claim 15, further comprising forming a flux layer in the first region of the PPI.

### Claim 20 (depends on 19)

The method of manufacturing a semiconductor package in claim 19, wherein annealing the PPI with is performed concurrently with forming the flux layer in the first region of the PPI.