# US 10,312,205 B2 · Fan-out semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,205 B2 - Document ID: US10312205B2 - Status: Granted - Kind: B2 - Application number: 15/606,467 - Filed: 2017-05-26 - Published: 2017-12-28 - Granted: 2019-06-04 - Earliest claimed: 2016-06-23 - Assignees: Samsung Electro-Mechanics Co., Ltd. - Applicants: Samsung Electro-Mechanics Co., Ltd. - Inventors: Youn Gyu Han - Web page: https://patentgrep.com/patent/US10312205B2 ## CPC - H10W 72/90: Bond pads, in general - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 40/778: {in encapsulations} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/69: Insulating materials thereof - H10W 72/00: Interconnections or connectors in packages - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/635: {Through-vias} - H10W 70/652: Cross-sectional shapes - H10W 70/655: Fan-out layouts - H10W 70/66: Conductive materials thereof - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9413: {on encapsulations} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A fan-out semiconductor package includes a semiconductor chip having an active surface, the active surface having a connection pad disposed thereon, and an inactive surface opposing the active surface; an encapsulant encapsulating at least a portion of the semiconductor chip; an insulating layer disposed on the active surface of the semiconductor chip; and a redistribution layer disposed on the insulating layer and electrically connected to the connection pad. The insulating layer includes a low tan delta (Df) dielectric material. ## Claims ### Claim 1 A semiconductor package comprising: a semiconductor chip having an active surface and an inactive surface opposing the active surface, the active surface having a connection pad disposed thereon; an encapsulant encapsulating at least a portion of the semiconductor chip; an insulating layer disposed on the active surface of the semiconductor chip, wherein the connection pad is disposed between the insulating layer and the inactive surface; a redistribution layer disposed on the insulating layer and electrically connected to the connection pad; and a heat dissipation member partially embedded in the encapsulant, disposed on a lateral portion of the semiconductor chip, and disposed on a level between the inactive surface of the semiconductor chip and the insulating layer, wherein the heat dissipation member is electrically isolated from the redistribution layer and the connection pad of the semiconductor chip. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the encapsulant exposes an upper surface of the heat dissipation member. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein an upper surface of the encapsulant is disposed on the same level as the upper surface of the heat dissipation member. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein the heat dissipation member penetrates through the encapsulant and is in contact with the insulating layer. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the insulating layer comprises a dielectric material having a tan delta of 0.0001 to 0.006. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein a surface of the insulating layer has a surface roughness (Ra) of 0.10 μm or less, and the redistribution layer is disposed on the surface having Ra of 0.10 μm or less. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the dielectric material comprises at least one of polyimide (PI), cycloolefinpolymer (COP), polyphenyleneoxide (PPO), polyphenyleneether (PPE), epoxy-cyanate ester, and liquid crystal polymer (LCP). ### Claim 8 (depends on 1) The semiconductor package of claim 1, further comprising: a passivation layer disposed on the insulating layer and having an opening portion exposing at least a portion of the redistribution layer; an under-bump metal layer disposed on the opening portion of the passivation layer; and connection terminals disposed on the under-bump metal layer and electrically connected to the redistribution layer, wherein at least one of the connection terminals is disposed in a fan-out region. ### Claim 9 (depends on 8) The semiconductor package of claim 8, further comprising: a surface mount technology (SMT) component disposed on a surface of the passivation layer and electrically connected to the semiconductor chip. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein the insulating layer comprises a first surface contacting the encapsulant and a second surface opposing the first surface, the redistribution layer comprises a first redistribution layer and a second redistribution layer disposed on the first surface and the second surface, respectively, and the first redistribution layer and the second redistribution layer are electrically connected to each other through a via passing through the insulating layer.