# US 10,312,203 B2 · Structure and formation method of chip package with antenna element > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,203 B2 - Document ID: US10312203B2 - Status: Granted - Kind: B2 - Application number: 15/625,678 - Filed: 2017-06-16 - Published: 2018-06-14 - Granted: 2019-06-04 - Earliest claimed: 2016-12-13 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co. Ltd. - Inventors: Yung-Ping Chiang; Nien-Fang Wu; Min-Chien Hsiao; Yi-Che Chiang; Chao-Wen Shih; Shou-Zen Chang; Chung-Shi Liu; Chen-Hua Yu - Web page: https://patentgrep.com/patent/US10312203B2 ## CPC - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H01Q 9/045: {with particular feeding means (for circular polarisation H01Q9/0428)} - H01Q 21/0087: {Apparatus or processes specially adapted for manufacturing antenna arrays (manufacturing waveguides H01P11/00)} - H01Q 21/065: {Patch antenna array} - H10P 72/74: {using temporarily an auxiliary support} - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/30: Die-attach connectors - H10W 72/90: Bond pads, in general - H10W 74/114: {by a substrate and the encapsulations} - H10W 90/00: Package configurations - H01Q 1/2283: {mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package} - H01Q 21/0075: {Stripline fed arrays (H01Q21/065 takes precedence)} - H01Q 21/22: Antenna units of the array energised non-uniformly in amplitude or phase, e.g. tapered array or binomial array - H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes} - H10P 72/7418: {of passive members, e.g. a chip mounting substrate} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto} - H10W 44/226: {for HF amplifiers} - H10W 44/248: {for antennas} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/652: Cross-sectional shapes - H10W 70/655: Fan-out layouts - H10W 72/0198: {batch processes} - H10W 72/073: {of die-attach connectors} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/874: {On different surfaces} - H10W 72/931: {Shapes of bond pads} - H10W 72/9413: {on encapsulations} - H10W 72/983: {Reinforcing structures, e.g. collars} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die. ## Claims ### Claim 1 A method for forming a chip package, comprising: forming a first conductive feature over a support substrate; disposing a semiconductor die over the support substrate; forming a first protective layer over the support substrate to surround the semiconductor die and the first conductive feature; replacing the support substrate with a second protective layer; disposing a conductive pin in the second protective layer; forming an antenna element over the second protective layer, wherein the antenna element is electrically connected to the conductive pin; and forming electrical connection between a conductive element of the semiconductor die and the antenna element through the first conductive feature. ### Claim 2 (depends on 1) The method for forming a chip package as claimed in claim 1, further comprising: forming an opening in the second protective layer; and forming a second conductive feature in the opening to be electrically connected to the first conductive feature, wherein the second conductive feature is electrically connected to the antenna element, and is electrically connected to the conductive element of the semiconductor die through the first conductive feature. ### Claim 3 (depends on 1) The method for forming a chip package as claimed in claim 1, further comprising: forming an opening in the second protective layer; printing a conductive paste over the second protective layer to fill the opening; and curing the conductive paste to form a conductive layer, wherein the conductive layer has a first portion over the second protective layer and a second portion filling the opening, the first portion forms the antenna element, and the second portion forms a second conductive feature. ### Claim 4 (depends on 3) The method for forming a chip package as claimed in claim 3, wherein the conductive pin is installed in the opening before printing the conductive paste. ### Claim 5 (depends on 4) The method for forming a chip package as claimed in claim 4, wherein the conductive pin has a lower portion and an upper portion, the lower portion is between the upper portion and the first protective layer, and the lower portion is wider than the upper portion. ### Claim 6 (depends on 1) The method for forming a chip package as claimed in claim 1, further comprising: forming an opening in the second protective layer; and forming a conductive layer over the first protective layer, wherein the conductive layer has a first portion over the second protective layer and a second portion extending into the opening, the first portion forms the antenna element, and the second portion forms a second conductive feature. ### Claim 7 (depends on 6) The method for forming a chip package as claimed in claim 6, wherein the conductive layer is formed using an electroplating process, an electroless plating process, or a combination thereof. ### Claim 8 (depends on 6) The method for forming a chip package as claimed in claim 6, wherein the conductive pin is installed in the opening before the conductive layer is formed, and the method further comprises: forming a seed layer on the conductive pin before the conductive layer is formed. ### Claim 9 (depends on 1) The method for forming a chip package as claimed in claim 1, further comprising: disposing a second semiconductor die over the support substrate before the first protective layer is formed, wherein after the first protective layer is formed, the first protective layer surrounds the second semiconductor die. ### Claim 10 (depends on 1) The method for forming a chip package as claimed in claim 1, wherein the second protective layer has a lower dielectric constant than that of the first protective layer. ### Claim 11 (depends on 1) The method for forming a chip package as claimed in claim 1, wherein the second protective layer has a lower dissipation factor than that of the first protective layer. ### Claim 12 (depends on 1) The method for forming a chip package as claimed in claim 1, further comprising forming a shielding element over the support substrate before the semiconductor die is disposed, wherein the semiconductor die covers a portion of the shielding element after the semiconductor die is disposed. ### Claim 13 (depends on 12) The method for forming a chip package as claimed in claim 12, wherein the shielding element is electrically isolated from the antenna element. ### Claim 14 A method for forming a chip package, comprising: forming a first conductive feature over a support substrate; disposing a semiconductor die over the support substrate; forming a first protective layer over the support substrate to surround the semiconductor die and the first conductive feature; removing the support substrate; forming a second protective layer over the first protective layer; disposing a conductive pin in the second protective layer; forming an antenna element over the second protective layer, wherein the antenna element is electrically connected to the conductive pin; and forming electrical connection between a conductive element of the semiconductor die and the antenna element through the first conductive feature. ### Claim 15 (depends on 14) The method for forming a chip package as claimed in claim 14, further comprising: forming an opening in the second protective layer; and forming a second conductive feature in the opening to be electrically connected to the first conductive feature, wherein the second conductive feature is electrically connected to the antenna element, and is electrically connected to the conductive element of the semiconductor die. ### Claim 16 (depends on 14) The method for forming a chip package as claimed in claim 14, further comprising: forming an opening in the second protective layer; printing a conductive paste over the second protective layer to fill the opening; and curing the conductive paste to form a conductive layer, wherein the conductive layer has a first portion over the second protective layer and a second portion filling the opening, the first portion forms the antenna element, and the second portion electrically connects the antenna element and the conductive element of the semiconductor die. ### Claim 17 (depends on 16) The method for forming a chip package as claimed in claim 16, wherein the conductive pin is installed in the opening before printing the conductive paste. ### Claim 18 (depends on 14) The method for forming a chip package as claimed in claim 14, wherein the conductive pin has a lower portion and an upper portion, the lower portion is between the upper portion and the first protective layer, and the lower portion is wider than the upper portion. ### Claim 19 A method for forming a chip package, comprising: forming a conductive feature over a support substrate; disposing a semiconductor die over the support substrate; forming a first protective layer to surround the semiconductor die and the conductive feature; forming a second protective layer over the first protective layer; disposing a conductive pin in the second protective layer; forming an antenna element over the second protective layer, wherein the second protective layer is between the antenna element and the semiconductor die, and the antenna element is electrically connected to the conductive pin; and forming electrical connection between a conductive element of the semiconductor die and the antenna element through the conductive feature. ### Claim 20 (depends on 19) The method for forming the chip package as claimed in claim 19, further comprising: forming an opening in the second protective layer; and forming a conductive layer over the second protective layer, wherein a first portion of the conductive layer extends into the opening, and a second portion of the conductive layer forms the antenna element.