# US 10,312,202 B2 · Zero capacitance electrostatic discharge devices

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- Number: US 10,312,202 B2
- Document ID: US10312202B2
- Status: Granted
- Kind: B2
- Application number: 15/805,897
- Filed: 2017-11-07
- Published: 2019-05-09
- Granted: 2019-06-04
- Earliest claimed: 2017-11-07
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: He Lin
- Web page: https://patentgrep.com/patent/US10312202B2

## CPC

- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 8/20: Breakdown diodes, e.g. avalanche diodes
- H10D 8/50: PIN diodes
- H10D 62/815: of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
- H10D 62/8171: {Doping structures, e.g. doping superlattices or nipi superlattices}
- H10D 89/611: {using diodes as protective elements}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In some examples, an electrostatic discharge (ESD) device includes a substrate layer, a transition layer positioned on the substrate layer, a plurality of superlattice layers on the transition layer and including at least two doped superlattice layers. The ESD device further includes a plurality of doped contact structures extending from the transition layer to a surface of an outermost layer of the plurality of superlattice layers, where a first of the plurality of doped contact structures comprises an anode and a second of the plurality of doped contact structures comprises a cathode, where the plurality of doped contact structures are to generate a zero capacitance ESD device.

## Claims

### Claim 1

A method of fabricating an electrostatic discharge (ESD) device, comprising:
providing a substrate layer;
depositing a transition layer on the substrate layer;
growing a first intrinsic superlattice layer on the transition layer;
growing a first-doped superlattice layer on the first intrinsic superlattice layer;
growing a second intrinsic superlattice layer on the first-doped superlattice layer;
growing a second-doped superlattice layer on the second intrinsic superlattice layer, wherein the second-doped superlattice layer has an outer surface;
implanting a first contact structure extending from the outer surface of the second-doped superlattice layer to the transition layer; and
implanting a second contact structure extending from the outer surface of the second-doped superlattice layer to the transition layer, wherein the first contact structure and the second contact structure are to receive a threshold voltage to generate a zero capacitance ESD device.

### Claim 2 (depends on 1)

The method of fabricating the ESD device of claim 1, further comprising:
trench-patterning a first isolation layer; and
trench-patterning a second isolation layer, wherein a distance between the first and second trench isolation layers is more than a distance between the first and second contact structures.

### Claim 3 (depends on 1)

The method of fabricating the ESD device of claim 1, further comprising:
depositing a passivation layer on the outer surface of the second-doped superlattice layer; and
patterning the passivation layer to deposit a first contact metal and a second contact metal to the first contact structure and the second contact structure, respectively.

### Claim 4 (depends on 1)

The method of fabricating the ESD device of claim 1, wherein the first-doped superlattice layer is a p-doped superlattice layer and the second-doped superlattice layer is an n-doped superlattice layer.

### Claim 5 (depends on 1)

The method of fabricating the ESD device of claim 1, wherein the first-doped superlattice layer is an n-doped superlattice layer and the second-doped superlattice layer is an n-doped superlattice layer.

### Claim 6 (depends on 1)

The method of fabricating the ESD device of claim 1, wherein the first-doped superlattice layer is an n-doped superlattice layer and the second-doped superlattice layer is a p-doped superlattice layer.

### Claim 7 (depends on 1)

The method of fabricating the ESD device of claim 1, wherein the transition layer includes material selected from the group consisting of Aluminum nitride, Silicon carbide, Gallium nitride, Gallium nitride, Gallium aluminum nitride, Gallium arsenide, Gallium aluminum arsenide, Aluminum arsenide, Cadmium telluride, Gallium antimonide, Gallium arsenide phosphide, Gallium manganese arsenide, Gallium phosphide, Indium arsenide, Indium gallium arsenide, Indium phosphide.