# US 10,312,200 B2 · Integrated circuit security

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- Number: US 10,312,200 B2
- Document ID: US10312200B2
- Status: Granted
- Kind: B2
- Application number: 15/662,258
- Filed: 2017-07-27
- Published: 2019-01-31
- Granted: 2019-06-04
- Earliest claimed: 2017-07-27
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kafai Lai; Rasit O Topaloglu
- Web page: https://patentgrep.com/patent/US10312200B2

## CPC

- H10W 42/40: protecting against tampering, e.g. unauthorised inspection or reverse engineering
- H10P 72/0614: {Marking devices}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- B65D 33/16: End- or aperture-closing arrangements or devices (valves of valve bags {B65D31/14}; closures of filled bags B65D77/10)
- B65D 33/28: Strings or strip-like closures {, i.e. draw closures}
- G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 2115/06: Structured ASICs
- G06F 2115/08: Intellectual property [IP] blocks or IP cores
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- H03K 19/195: using superconductive devices
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/401: {for identification or tracking}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B65D: CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A semiconductor product includes a substrate having a self-assembly (SA) pattern. An initial SA pattern is created using a block copolymer (BCP) which has been annealed on the substrate. The initial SA pattern and/or an enlarged SA pattern derived from the initial SA pattern is incorporated into the semiconductor product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product. In other embodiments of the invention a method and system for creating the semiconductor product are described.

## Claims

### Claim 1

A semiconductor product comprising:
a substrate having a self-assembly (SA) pattern, wherein the SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate, wherein the SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.

### Claim 2 (depends on 1)

The semiconductor product as recited in claim 1, wherein the substrate is a semiconductor chip and the initial SA pattern has been created on an upper, physically observable layer.

### Claim 3 (depends on 2)

The semiconductor product as recited in claim 2, wherein the semiconductor chip is attached to a package so that the initial SA pattern is a physically observable security feature.

### Claim 4 (depends on 1)

The semiconductor product as recited in claim 1, further comprising a package having an enlarged SA pattern, the enlarged SA pattern derived from the initial SA pattern, wherein the substrate is a semiconductor chip attached to the package.

### Claim 5 (depends on 4)

The semiconductor product as recited in claim 4, wherein the package has an opening where the enlarged SA pattern is located and can be optically observed.

### Claim 6 (depends on 1)

The semiconductor product as recited in claim 1, further comprising a package on which a semiconductor chip having an enlarged SA pattern is attached, the enlarged SA pattern derived from the initial SA pattern.

### Claim 7

A method for manufacturing a semiconductor product comprising:
creating a self-assembly (SA) pattern on a substrate, wherein the SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate;
scanning the SA pattern to capture an image of the SA pattern;
storing data from the SA pattern in a computer system; and
providing the SA pattern on the semiconductor product;
wherein the SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.

### Claim 8 (depends on 7)

The method as recited in claim 7, wherein the substrate is a semiconductor chip and the initial SA pattern has been created on an upper, physically observable layer.

### Claim 9 (depends on 7)

The method as recited in claim 7, wherein the substrate is a semiconductor chip and the method further comprises:
generating an enlarged SA pattern from the SA pattern; and
creating the enlarged SA pattern on the semiconductor product.

### Claim 10 (depends on 9)

The method as recited in claim 9, further comprising:
providing a first layer and a second layer on a semiconductor chip, wherein the second layer is disposed on top of the first layer and is selected to provide an optical contrast to the first layer;
providing a lithographic pattern on the second layer, the lithographic pattern a version of the enlarged SA pattern; and
etching through exposed portions of the second layer to create the enlarged SA pattern on the semiconductor chip.

### Claim 11 (depends on 7)

The method as recited in claim 7, further comprising:
storing a set of features and feature locations within the SA pattern;
associating the set of features and feature locations with the semiconductor product.

### Claim 12 (depends on 11)

The method as recited in claim 11, wherein the set of features are selected from the group consisting of line end features, fork features and short-line features.

### Claim 13 (depends on 7)

The method as recited in claim 7, further comprising:
receiving a set of features and feature locations from a customer;
verifying the received set of features and feature locations as associated with the semiconductor product.

### Claim 14 (depends on 13)

The method as recited in claim 13, wherein the set of features and feature locations are stored efficiently using a sparse matrix representation and wherein the received set of features and feature locations are used to verify a customer semiconductor product against a SA pattern database using an elastic string match utilizing an edit distance metric to compare the stored set of features and feature locations with the received set of features and feature locations.

### Claim 15

Apparatus, comprising:
a processor;
a scanner;
a computer memory holding computer program instructions executed by the processor, the computer program instructions comprising:
program code, operative to receive an image of a self-assembly (SA) pattern on a substrate from the scanner, wherein the SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate;
program code, operative to store data from the SA pattern in a computer system; and
program code, operative to associate the SA pattern data with the semiconductor product;
wherein the SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.

### Claim 16 (depends on 15)

The apparatus recited in claim 15, wherein the substrate is a semiconductor chip and the computer program instructions further comprise:
program code, operative to generate an enlarged SA pattern from the SA pattern;
program code, operative to store SA pattern data about the enlarged SA pattern in the computer memory; and
program code, operative to associate the SA pattern data about the enlarged SA pattern with the semiconductor product.

### Claim 17 (depends on 16)

The apparatus as recited in claim 16, wherein the program code, operative to generating an enlarged SA pattern from the SA pattern further comprises:
program code, operative to invert the SA pattern image;
program code, operative to clarify scanned lines from the SA pattern image; and
program code, operative to add a registration mark to the enlarged SA pattern.

### Claim 18 (depends on 15)

The apparatus as recited in claim 15, wherein the SA pattern data is a set of features and feature locations from the SA image and the computer program instructions further comprise:
program code, operative to receive a set of features and feature locations from a customer;
program code, operative to verify the received set of features and feature locations as associated with the semiconductor product by matching the received set of features and feature locations with the stored features and feature locations.

### Claim 19 (depends on 15)

The apparatus as recited in claim 15, wherein the scanner is a scanning electron microscope.

### Claim 20 (depends on 15)

The apparatus as recited in claim 15 further comprising program code operative to associate the SA pattern data with model and serial numbers information.