# US 10,312,197 B2 · Method of manufacturing semiconductor device and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,197 B2 - Document ID: US10312197B2 - Status: Granted - Kind: B2 - Application number: 14/475,326 - Filed: 2014-09-02 - Published: 2015-06-18 - Granted: 2019-06-04 - Earliest claimed: 2013-12-13 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Yuusuke Takano; Takashi Imoto; Takeshi Watanabe; Soichi Homma; Katsunori Shibuya - Web page: https://patentgrep.com/patent/US10312197B2 ## CPC - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 46/101: {characterised by the type of information, e.g. logos or symbols} - H10W 46/103: {alphanumeric information, e.g. words, letters or serial numbers} - H10W 46/401: {for identification or tracking} - H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates} - H10W 72/0198: {batch processes} - H10W 72/5366: {the bond wires having kinks} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/014: {using batch processing} - H10W 74/473: {containing a filler} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract According to one embodiment, a method of manufacturing a semiconductor device includes forming a sealing resin layer containing an inorganic filler so as to seal a semiconductor chip, removing a portion of the surface of the sealing resin layer by dry etching such that a portion of the inorganic filler is exposed, and forming a shield layer so as to cover at least the sealing resin layer. ## Claims ### Claim 1 A method of manufacturing a semiconductor device, the method comprising: mounting a plurality of semiconductor chips on a surface of a wiring board; enclosing the plurality of semiconductor chips on the surface of the wiring board in a sealing resin comprising an inorganic filler and an organic resin; cutting the wiring board and the sealing resin into a plurality of sealing resin layers each having at least one semiconductor chip therein; placing a separated sealing resin layer in a vacuum environment; removing a portion of the separated sealing resin layer by dry etching such that a portion of inorganic filler exposed at front and side surfaces of the sealing resin layer to form irregularities on the front and side surfaces of the sealing resin, the dry etching being carried out by sputter etching the surfaces of the at least one separated sealing resin layer within the vacuum environment; and forming a shield layer on the separated sealing resin layer by sputter deposition in the vacuum environment, the shield layer contacting the exposed portion of the inorganic filler on the front and side surfaces of the separated sealing resin layer, the shield layer being formed without removing the separated sealing resin layer from the vacuum environment after the dry etching. ### Claim 2 (depends on 1) The method according to claim 1, further comprising forming a protective layer on the shield layer after forming the shield layer. ### Claim 3 (depends on 2) The method of claim 2, wherein the protective layer comprises a material having a greater corrosion resistance and electro-migration resistance than a material comprising the shield layer. ### Claim 4 (depends on 1) The method of claim 1, further comprising depositing wherein the shield layer is deposited such that a sheet resistance value thereof is 0.5Ω or less, the sheet resistance value being a value obtained by dividing an electrical resistivity of the shield layer by a thickness of the shield layer. ### Claim 5 (depends on 1) The method of claim 1, wherein the shield layer comprises copper. ### Claim 6 (depends on 1) The method of claim 1, wherein the semiconductor chip is mounted on the wiring board such that the semiconductor chip is electrically connected to a via extending through a thickness of the wiring board, the via being connected to a conductor of the wiring board extending to an edge of the wiring board; and the shield layer is electrically connected to the conductor of the wiring board at the edge of the wiring board. ### Claim 7 (depends on 6) The method of claim 6, wherein the conductor of the wiring board is a conductive mesh extending to the edge of the wiring board. ### Claim 8 (depends on 6) The method of claim 6, wherein the conductor of the wiring board is a solid film extending to the edge of the wiring board. ### Claim 9 (depends on 7) The method of claim 7, wherein the conductor is within an interior of the wiring board. ### Claim 10 (depends on 8) The method of claim 8, wherein the conductor is within an interior of the wiring board. ### Claim 11 (depends on 1) The method of claim 1, wherein the inorganic filler is a particulate. ### Claim 12 (depends on 1) The method of claim 1, wherein the dry etching is performed for at least 100 seconds, but less than 300 seconds. ### Claim 13 A method of manufacturing a semiconductor device, the method comprising: mounting a plurality of semiconductor chips on a surface of a substrate, the substrate including an inner conductive layer electrically connected to a ground terminal of each semiconductor chip using at least one via exposed at the surface of the substrate; covering the plurality of semiconductor chips on the surface of the substrate with a sealing resin comprising an inorganic filler and an organic resin; cutting the sealing resin and the substrate to form a plurality of sealing resin layers, each having a semiconductor chip therein, the inner conductive layer of the substrate being exposed at a side edge of each sealing resin layer; placing a separated sealing resin layer in a vacuum environment; reverse sputter etching the front and side surfaces of the separated sealing layer in the vacuum environment to remove portions of the separated sealing layer to a depth between 2.5 nm and 7.5 nm such that a portion of the inorganic filler is exposed at the front and side surfaces of the separated sealing resin layer and irregularities are formed on the front and side surfaces of the separated sealing resin layer; and forming a shield layer on the separated sealing resin layer by sputter deposition in the vacuum environment, the shield layer contacting the exposed portion of the inorganic filler and being electrically connected to the inner conductive layer at the side edge of the separated sealing resin layer, the shield layer being formed without removing the separated sealing resin layer from the vacuum environment after reverse sputter etching the separated sealing resin layer. ### Claim 14 (depends on 13) The method of claim 13, further comprising: ashing an entire surface of the separated sealing resin layer in the vacuum environment after the reverse sputter etching. ### Claim 15 (depends on 13) The method of to claim 13, further comprising forming a protective layer on the shield layer. ### Claim 16 (depends on 13) The method of claim 13, wherein the shield layer is deposited such that a sheet resistance value thereof is 0.5Ω or less, the sheet resistance value being a value obtained by dividing an electrical resistivity of the shield layer by a thickness of the shield layer. ### Claim 17 (depends on 13) The method of claim 13, wherein the inorganic filler is a particulate. ### Claim 18 (depends on 13) The method of claim 13, wherein the inner conductive layer is a mesh embedded within the substrate. ### Claim 19 (depends on 13) The method of claim 13, wherein the vacuum environment is a sputter chamber.