# US 10,312,196 B2 · Semiconductor packages including indicators for evaluating a distance and methods of calculating the distance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,196 B2 - Document ID: US10312196B2 - Status: Granted - Kind: B2 - Application number: 15/945,989 - Filed: 2018-04-05 - Published: 2019-01-17 - Granted: 2019-06-04 - Earliest claimed: 2017-07-17 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Sukwon Lee; Bok Gyu Min - Web page: https://patentgrep.com/patent/US10312196B2 ## CPC - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10W 90/00: Package configurations - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 46/101: {characterised by the type of information, e.g. logos or symbols} - H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates} - H10W 72/0198: {batch processes} - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/014: {using batch processing} - H10W 90/20: Configurations of stacked chips - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package may include a package substrate to which a first semiconductor chip is attached, an encapsulant covering the first semiconductor chip, and an indicator disposed within the semiconductor package. A side surface of the indicator is exposed at a side surface of the semiconductor package, and a width of a vertical section of the indicator parallel with the exposed side surface of the indicator varies as the vertical section of the indicator becomes farther from the side surface of the semiconductor package. ## Claims ### Claim 1 A semiconductor package comprising: a package substrate to which a first semiconductor chip is attached; an encapsulant covering the first semiconductor chip; and an indicator including an array of indicating blocks disposed within the semiconductor package, wherein at least one of the indicating blocks is exposed at a side surface of the semiconductor package, and wherein the number of the indicating blocks exposed by a vertical section of the indicator parallel with the side surface of the semiconductor package varies as the vertical section of the indicator becomes farther from the side surface of the semiconductor package. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the indicator is disposed in the package substrate. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the indicator is disposed on the package substrate. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein the indicating blocks are arrayed in a plurality of columns which are sequentially disposed from the side surface of the semiconductor package toward the first semiconductor chip. ### Claim 5 (depends on 4) The semiconductor package of claim 4, wherein the indicating blocks disposed in two adjacent columns among the plurality of columns are arrayed in a zigzag fashion along a length direction of the plurality of columns. ### Claim 6 (depends on 4) The semiconductor package of claim 4, wherein the indicating blocks arrayed in each of the plurality of columns are spaced apart from each other by substantially the same distance. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein each of the indicating blocks includes a rectangular pattern; and wherein the indicating blocks are substantially the same size. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the indicating blocks are arrayed in first to third columns which are sequentially disposed from the side surface of the semiconductor package toward the first semiconductor chip; and wherein the number of the indicating blocks arrayed in the first column, the number of the indicating blocks arrayed in the second column, and the number of the indicating blocks arrayed in the third column are different from each other. ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein the number of the indicating blocks which are exposed at the side surface of the semiconductor package varies according a distance between the side surface of the semiconductor package and the first semiconductor chip. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein the indicating blocks are disposed between the encapsulant and the package substrate. ### Claim 11 (depends on 1) The semiconductor package of claim 1, wherein the package substrate includes interconnection patterns; and wherein the indicating blocks are located at the same level as the interconnection structure. ### Claim 12 (depends on 1) The semiconductor package of claim 1, further comprising a second semiconductor chip which is stacked on the first semiconductor chip and is offset from the first semiconductor chip. ### Claim 13 (depends on 1) The semiconductor package of claim 1, further comprising: an additional semiconductor chip disposed between the first semiconductor chip and the package substrate; and a supporting part disposed between the first semiconductor chip and the package substrate to support the first semiconductor chip and to provide a cavity in which the additional semiconductor chip is disposed.