# US 10,312,195 B2 · Fan-out semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,195 B2 - Document ID: US10312195B2 - Status: Granted - Kind: B2 - Application number: 15/819,541 - Filed: 2017-11-21 - Published: 2019-01-17 - Granted: 2019-06-04 - Earliest claimed: 2017-07-14 - Assignees: Samsung Electro-Mechanics Co., Ltd. - Applicants: Samsung Electro-Mechanics Co., Ltd. - Inventors: Ji Hyun Lee; Jin Gu Kim; Chang Bae Lee; Jin Su Kim - Web page: https://patentgrep.com/patent/US10312195B2 ## CPC - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/68: Shapes or dispositions thereof - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/9413: {on encapsulations} - H10W 90/00: Package configurations - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of degassing holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of degassing holes when being projected in a direction perpendicular to the active surface. ## Claims ### Claim 1 A semiconductor package comprising: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; and a first connection member disposed on the active surface of the semiconductor chip, and including a first insulating layer disposed on the active surface of the semiconductor chip, a first redistribution layer made of an electrically conductive material and electrically connected to the connection pads through vias in the first insulating layer, a second insulating layer covering the first redistribution layer, and a second redistribution layer electrically connected to the connection pads through at least the first redistribution layer and being in contact with the second insulating layer, wherein the first redistribution layer includes a first conductive pattern having a plurality of holes exposing portions of the first insulating layer, respectively, the second insulating layer fills the plurality of holes and is in contact with the portions of the first insulating layers exposed by the plurality of holes, when viewed in a direction perpendicular to the active surface, the second redistribution layer includes a second conductive pattern having a first line portion having a first line width and a second line portion extending from the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of holes when being projected in the direction perpendicular to the active surface. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the first conductive pattern is a ground pattern and the second conductive pattern is a signal pattern. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the first conductive pattern is a single integral pattern having the plurality of holes surrounded by an outer boundary of the first conductive pattern. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein the second conductive pattern extends across the first conductive pattern when being projected in the direction perpendicular to the active surface. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the plurality of holes are degassing holes. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein when viewed in the direction perpendicular to the active surface, a line width of the second conductive pattern is changed from the first line width of the first line portion to the second line width of the second line portion before the second conductive pattern passes through a region in which the second line portion overlaps the at least one of the plurality of holes, and is changed from the second line width of the second line portion to the first line width of the first line portion after the second conductive pattern passes through the region. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the first conductive pattern and the second conductive pattern include copper (Cu). ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the second insulating layer includes recesses recessed toward the plurality of holes, respectively. ### Claim 9 (depends on 1) The semiconductor package of claim 1, further comprising: a second connection member having a through-hole, in which the semiconductor chip is disposed; and an encapsulant encapsulating at least portions of the semiconductor chip and the second connection member, and filling portions of the through-hole. ### Claim 10 (depends on 9) The semiconductor package of claim 9, wherein the second connection member includes a third insulating layer, a first wiring layer in contact with the first connection member and embedded in the third insulating layer, and a second wiring layer disposed on the other surface of the third insulating layer opposing one surface of the third insulating layer in which the first wiring layer is embedded, and the first and second wiring layers are electrically connected to the connection pads. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein the second connection member further includes a fourth insulating layer disposed on the third insulating layer and covering the second wiring layer and a third wiring layer disposed on the fourth insulating layer, and the third wiring layer is electrically connected to the connection pads. ### Claim 12 (depends on 10) The semiconductor package of claim 10, wherein a lower surface of the first wiring layer has a step with respect to a lower surface of the third insulating layer. ### Claim 13 (depends on 9) The semiconductor package of claim 9, wherein the second connection member includes a third insulating layer, a first wiring layer and a second wiring layer disposed on opposite surfaces of the third insulating layer, respectively, a fourth insulating layer disposed on the third insulating layer and covering the first wiring layer, and a third wiring layer disposed on the fourth insulating layer, and the first to third wiring layers are electrically connected to the connection pads. ### Claim 14 (depends on 13) The semiconductor package of claim 13, wherein the second connection member further includes a fifth insulating layer disposed on the third insulating layer and covering the second wiring layer and a fourth wiring layer disposed on the fifth insulating layer, and the fourth wiring layer is electrically connected to the connection pads. ### Claim 15 (depends on 13) The semiconductor package of claim 13, wherein the third insulating layer has a thickness greater than that of the fourth insulating layer. ### Claim 16 A semiconductor package comprising: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the active surface of the semiconductor chip, and including a first insulating layer disposed on the active surface of the semiconductor chip, a first redistribution layer made of an electrically conductive material and electrically connected to the connection pads through vias in the first insulating layer, a second insulating layer covering the first redistribution layer, and a second redistribution layer electrically connected to the connection pads through at least the first redistribution layer and being in contact with the second insulating layer, wherein the first redistribution layer includes a first conductive pattern having a plurality of holes exposing portions of the first insulating layer, respectively, and a second conductive pattern disposed inside one of the plurality of holes, the second insulating layer fills the plurality of holes and is in contact with the portions of the first insulating layers exposed by the plurality of holes, the second distribution layer includes a third conductive pattern, and the third conductive pattern overlaps with the second conductive pattern, when being projected in a direction perpendicular to the active surface. ### Claim 17 (depends on 16) The semiconductor package of claim 16, wherein the second conductive pattern is spaced apart from the one of the plurality of holes. ### Claim 18 (depends on 16) The semiconductor package of claim 16, wherein the one of the plurality of holes is separated into a plurality of sub-holes by the second conductive pattern. ### Claim 19 A semiconductor package comprising: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the active surface of the semiconductor chip, and including a first insulating layer disposed on the active surface of the semiconductor chip, a first redistribution layer made of electrically conductive material and electrically connected to the connection pads through vias in the first insulating layer, a second redistribution layer electrically connected to the connection pads through at least the first redistribution layer and disposed on the first redistribution layer, and a second redistribution layer electrically connected to connection pads through at least the first redistribution layer and being in contact second insulating layer, wherein the first redistribution layer includes a first conductive continuous pattern having a plurality of holes surrounded by an outer boundary of the first conductive continuous pattern, the plurality of holes expose portions of the first insulating layer, respectively, the second insulating layer fills the plurality of holes and is in contact with the portions of the first insulating layers exposed by the plurality of holes, the second distribution layer includes a second conductive pattern, and the second conductive pattern and the first conductive continuous pattern overlap with each other and the second conductive pattern is spaced apart from the plurality of holes, when being projected in a direction perpendicular to the active surface. ### Claim 20 (depends on 1) The semiconductor package of claim 1, further comprising: a passivation layer disposed on the first connection member and having openings exposing portions of conductive patterns of the first connection member; an underbump metal layer filling the openings in the passivation layer; and connection terminals disposed on the underbump metal layer and electrically connected to the conductive patterns of the first connection member, wherein at least one of the openings is disposed in a fan-out region.