# US 10,312,194 B2 · Stacked electronics package and method of manufacturing thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,194 B2 - Document ID: US10312194B2 - Status: Granted - Kind: B2 - Application number: 15/343,259 - Filed: 2016-11-04 - Published: 2018-05-10 - Granted: 2019-06-04 - Earliest claimed: 2016-11-04 - Assignees: General Electric Company - Applicants: General Electric Company - Inventors: Risto Ilkka Tuominen; Arun Virupaksha Gowda - Web page: https://patentgrep.com/patent/US10312194B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 90/00: Package configurations - H10W 70/654: Top-view layouts - H10W 70/655: Fan-out layouts - H10W 72/073: {of die-attach connectors} - H10W 72/074: {of anisotropic conductive adhesives} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/354: {comprising polymers} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An electronics package includes an insulating substrate, a first electrical component coupled to a top surface of the insulating substrate, and a second electrical component coupled to a bottom surface of the insulating substrate. A first conductor layer is formed on the bottom surface of the insulating substrate and extends through a via formed therethrough to contact a contact pad of the first electrical component, with a portion of the first conductor layer positioned between the insulating substrate and the second electrical component. A second conductor layer is formed on the top surface of the insulating substrate and extends through another via formed therethrough to electrically couple with the first conductor layer and to contact a contact pad of the second electrical component. ## Claims ### Claim 1 An electronics package comprising: an insulating substrate; a first electrical component coupled to a top surface of the insulating substrate; a second electrical component coupled to a bottom surface of the insulating substrate; a first conductor layer disposed over a portion of the bottom surface of the insulating substrate and extending through a via formed therethrough to contact a contact pad of the first electrical component; and a second conductor layer disposed over a portion of the top surface of the insulating substrate, extending through another via formed therethrough to electrically couple with the first conductor layer, and extending through yet another via formed therethrough to contact a contact pad of the second electrical component; wherein a portion of the first conductor layer is positioned between the insulating substrate and the second electrical component. ### Claim 2 (depends on 1) The electronics package of claim 1 wherein the first conductor layer is thinner than the second conductor layer. ### Claim 3 (depends on 1) The electronics package of claim 1 wherein the first electrical component comprises a digital semiconductor device; and wherein the second electrical component comprises a power semiconductor device. ### Claim 4 (depends on 1) The electronics package of claim 1 wherein the first electrical component has a greater number of contact pads than the second electrical component. ### Claim 5 (depends on 1) The electronics package of claim 1 wherein the first electrical component is thinner than the thickness of the second conductor layer. ### Claim 6 (depends on 1) The electronics package of claim 1 wherein an active surface of the first electrical component having at least one contact pad thereon is positioned facing an active surface of the second electrical component having at least one contact pad thereon. ### Claim 7 (depends on 1) The electronics package of claim 1 wherein the first electrical component and the second electrical component are arranged in a stacked configuration. ### Claim 8 (depends on 7) The electronics package of claim 7 wherein the first electrical component is aligned with the second electrical component along a common vertical axis. ### Claim 9 (depends on 1) The electronics package of claim 1 further comprising a redistribution layer formed atop and electrically coupled to the second conductor layer. ### Claim 10 (depends on 1) The electronics package of claim 1 wherein the bottom surface of the insulating substrate has an adhesion layer and a seed layer applied thereto. ### Claim 11 (depends on 1) The electronics package of claim 1 wherein the top surface of the insulating substrate has an adhesion layer and a seed layer applied thereto. ### Claim 12 A method of manufacturing an electronics package comprising: coupling a first electrical component to a top surface of an insulating substrate; forming a first conductor layer on a bottom surface of the insulating substrate, the first conductor layer extending through at least one via in the insulating substrate to electrically couple with at least one contact pad of the first electrical component; coupling a second electrical component to the bottom surface of the insulating substrate such that a portion of the first conductor layer is positioned therebetween; and forming a second conductor layer on a top surface of the insulating substrate, the second conductor layer extending through another via in the insulating substrate to electrically couple with the first conductor layer; wherein the second conductor layer is electrically coupled to at least one contact pad of the second electrical component. ### Claim 13 (depends on 12) The method of claim 12 further comprising forming the second conductor layer having a thickness greater than a thickness of the first conductor layer. ### Claim 14 (depends on 12) The method of claim 12 further comprising forming the second conductor layer to surround at least a portion of the first electrical component. ### Claim 15 (depends on 12) The method of claim 12 further comprising coupling the second electrical component such that active surface thereof faces an active surface of the first electrical component. ### Claim 16 (depends on 12) The method of claim 12 further comprising arranging the first electrical component and the second electrical component to at least partially overlap in a vertical direction. ### Claim 17 (depends on 12) The method of claim 12 further comprising: patterning the first conductor layer to define a high density L/S (line/space) routing pattern; and patterning the second conductor layer to define a low density L/S (line/space) routing pattern. ### Claim 18 (depends on 12) The method of claim 12 further comprising: applying an adhesion layer and a seed layer to the bottom surface of the insulating substrate prior to forming the first conductor layer; and applying an adhesion layer and a seed layer to the top surface of the insulating substrate prior to forming the second conductor layer. ### Claim 19 A stacked electronics package comprising: a pair of electrical components coupled to opposing surfaces of an insulating substrate in a stacked configuration wherein an active surface of one electrical component faces an active surface of the other electrical component; a first conductor layer coupled to a bottommost surface of the insulating substrate and extending through a via in the insulating substrate to electrically couple to one electrical component of the pair of electrical components; and a second conductor layer coupled to a topmost surface of the insulating substrate and extending through another via in the insulating substrate to electrically couple to the other electrical component of the pair of electrical components; wherein a portion of the first conductor layer is positioned between the pair of electrical components. ### Claim 20 (depends on 19) The stacked electronics package of claim 19 wherein the second conductor layer has a thickness greater than a thickness of the first conductor layer. ### Claim 21 (depends on 19) The stacked electronics package of claim 19 wherein the pair of electrical components comprises a digital semiconductor device and a power semiconductor device. ### Claim 22 (depends on 19) The stacked electronics package of claim 19 wherein the first conductor layer comprises a high density L/S (line/space) pattern; and wherein the second conductor layer comprises a low density L/S (line/space) pattern. ### Claim 23 (depends on 19) The stacked electronics package of claim 19 further comprising a redistribution layer formed atop the second conductor layer and electrically coupled thereto. ### Claim 24 (depends on 19) The stacked electronics package of claim 19 wherein at least one of the bottommost surface and the topmost surface of the insulating substrate have an adhesion layer and a seed layer applied thereto.