# US 10,312,189 B2 · Enhancing integrated circuit density with active atomic reservoir > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,189 B2 - Document ID: US10312189B2 - Status: Granted - Kind: B2 - Application number: 15/928,909 - Filed: 2018-03-22 - Published: 2018-08-02 - Granted: 2019-06-04 - Earliest claimed: 2015-11-16 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Ta-Pen Guo; Ming-Hsien Lin - Web page: https://patentgrep.com/patent/US10312189B2 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10D 1/00: Resistors, capacitors or inductors - H10D 62/102: {Constructional design considerations for preventing surface leakage or controlling electric field concentration} - H10D 84/907: {CMOS gate arrays} - H10D 89/10: Integrated device layouts - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 20/44: Conductive materials thereof - H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers} - H10D 84/975: {Wiring regions or routing} - H10D 84/979: {Data lines, e.g. buses} - H10D 84/981: {Power supply lines} - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 20/4405: {the principal metal being aluminium} - H10W 20/4421: {the principal metal being copper} - H10W 20/4432: {the principal metal being a noble metal, e.g. gold} - H10W 20/4441: {the principal metal being a refractory metal} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Methods are disclosed herein for fabricating integrated circuit interconnects that can improve electromigration. An exemplary method includes forming a first metal layer of an integrated circuit and forming a second metal layer of the integrated circuit. The first metal layer includes a first conductor electrically coupled to a second conductor, and the second metal layer includes a third conductor electrically coupled to the first conductor. The first conductor, the second conductor, and the third conductor are configured, such that electrons flow from the second conductor to an area of the first conductor where electrons flow from the third conductor to the first conductor. ## Claims ### Claim 1 A method comprising: forming a first metal layer of an integrated circuit, wherein the first metal layer includes a first conductor electrically coupled to a second conductor; forming a second metal layer of the integrated circuit, wherein the second metal layer includes a third conductor electrically coupled to the first conductor; and wherein the first conductor, the second conductor, and the third conductor are configured such that electrons flow from the second conductor to an area of the first conductor where electrons flow from the third conductor to the first conductor. ### Claim 2 (depends on 1) The method of claim 1, wherein the first conductor is oriented along a first direction, the third conductor is oriented along a second direction substantially perpendicular to the first direction, and the second conductor is oriented along the first direction. ### Claim 3 (depends on 1) The method of claim 1, wherein the first conductor is oriented along a first direction, the third conductor is oriented along a second direction substantially perpendicular to the first direction, and the second conductor is oriented along the second direction. ### Claim 4 (depends on 1) The method of claim 1, further comprising forming a via that electrically couples the first conductor to the third conductor. ### Claim 5 (depends on 4) The method of claim 4, wherein the via is a first via, the method further comprising forming a second via that electrically couples the second conductor to the third conductor. ### Claim 6 (depends on 4) The method of claim 4, wherein the forming the first metal layer and the forming the via includes performing a dual damascene process. ### Claim 7 (depends on 1) The method of claim 1, wherein the forming the first metal layer includes: forming at least one opening in a dielectric layer; and filling the at least one opening with an electrically conductive material. ### Claim 8 (depends on 7) The method of claim 7, wherein the filling the at least one opening with the electrically conductive material includes: depositing a metal diffusion barrier layer on portions of the dielectric layer defining sidewalls and a bottom of the at least one opening; and depositing a metal plug over the metal diffusion barrier layer. ### Claim 9 (depends on 1) The method of claim 1, wherein the forming the second metal layer includes: forming at least one opening in a dielectric layer; and filling the at least one opening with an electrically conductive material. ### Claim 10 (depends on 9) The method of claim 9, wherein the filling the at least one opening with the electrically conductive material includes: depositing a metal diffusion barrier layer on portions of the dielectric layer defining sidewalls and a bottom of the at least one opening; and depositing a metal plug over the metal diffusion barrier layer. ### Claim 11 A method comprising: forming a first wiring layer in a dielectric layer, wherein the first wiring layer includes a first conductor electrically coupled with a second conductor, wherein the second conductor is orientated substantially perpendicular to the first conductor; forming a second wiring layer in the dielectric layer, wherein the second wiring layer includes a third conductor oriented substantially perpendicular to the first conductor; and forming a via layer in the dielectric layer between the first wiring layer and the second wiring layer, wherein the via layer includes a first via that electrically couples the second conductor to the first conductor and a second via that electrically couples the second conductor to the third conductor. ### Claim 12 (depends on 11) The method of claim 11, wherein the forming the first wiring layer and the second wiring layer includes: forming a first dielectric layer of the dielectric layer over a substrate; performing a first lithography process to define a first trench in the first dielectric layer; filling the first trench with a metal material, thereby forming the third conductor in the first dielectric layer; forming a second dielectric layer of the dielectric layer over the first dielectric layer; performing a second lithography process to define a second trench in the second dielectric layer; and filling the second trench with a metal material, thereby forming the first conductor and the second conductor. ### Claim 13 (depends on 12) The method of claim 12, wherein the second trench includes lower portions that define the first via and the second via and upper portions that define the first conductor and the second conductor, such that the via layer is formed when the first wiring layer is formed. ### Claim 14 (depends on 12) The method of claim 12, wherein the first dielectric layer and the second dielectric layer include a low-k dielectric material, and the metal material includes tantalum, copper, aluminum, tungsten, cobalt, silver, gold, or combinations thereof. ### Claim 15 (depends on 11) The method of claim 11, further comprising forming a doped region in a substrate, wherein the dielectric layer is disposed over the substrate and the second conductor is electrically coupled to the doped region. ### Claim 16 A method comprising: forming a first wiring layer in a dielectric layer, wherein the first wiring layer includes a first conductor electrically coupled with a second conductor; forming a second wiring layer in the dielectric layer, wherein the second wiring layer includes a third conductor; and forming a via layer in the dielectric layer between the first wiring layer and the second wiring layer, wherein the via layer includes a first via that electrically couples the third conductor to the first conductor and a second via that electrically couples the second conductor with a voltage that is different than a voltage electrically coupled with the first conductor. ### Claim 17 (depends on 16) The method of claim 16, wherein the forming the first wiring layer and the second wiring layer includes: forming a first dielectric layer of the dielectric layer over a substrate; performing a first lithography process to define a first trench in the first dielectric layer; filling the first trench with a metal material, thereby forming the third conductor in the first dielectric layer; forming a second dielectric layer of the dielectric layer over the first dielectric layer; performing a second lithography process to define a second trench in the second dielectric layer; and filling the second trench with a metal material, thereby forming the first conductor and the second conductor. ### Claim 18 (depends on 17) The method of claim 17, wherein the second trench includes lower portions that define the first via and the second via and upper portions that define the first conductor and the second conductor, such that the via layer is formed when the first wiring layer is formed. ### Claim 19 (depends on 17) The method of claim 17, wherein the first dielectric layer and the second dielectric layer include a low-k dielectric material, and the metal material includes tantalum, copper, aluminum, tungsten, cobalt, silver, gold, or combinations thereof. ### Claim 20 (depends on 16) The method of claim 16, wherein the first conductor is oriented lengthwise along a first direction, the third conductor is oriented lengthwise along a second direction substantially perpendicular to the first direction, and the second conductor is oriented lengthwise along the first direction.