# US 10,312,188 B1 · Interconnect structure with method of forming the same

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- Number: US 10,312,188 B1
- Document ID: US10312188B1
- Status: Granted
- Kind: B1
- Application number: 15/867,894
- Filed: 2018-01-11
- Granted: 2019-06-04
- Earliest claimed: 2018-01-11
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Ravi P. Srivastava; Sunil K. Singh
- Web page: https://patentgrep.com/patent/US10312188B1

## CPC

- H10W 20/42: Vias, e.g. via plugs
- H10W 20/033: {in openings in dielectrics}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/085: {involving intermediate temporary filling with material}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10W 20/0886: {involving forming a via in a via-level dielectric prior to deposition of a trench-level dielectric}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit (IC) structure including an interconnect structure is disclosed. The interconnect structure may include a first etch stop layer (ESL) positioned between an initial via layer and a first metal layer of the interconnect structure. The ESL may be positioned adjacent to and surround a metal wire in the first metal layer. A method of forming an interconnect structure is also disclosed. The method may include forming an opening in a first dielectric layer above a substrate; forming a sacrificial semiconductor material in the opening; forming an ESL on the first dielectric layer and sacrificial semiconductor material; forming a second dielectric layer on the ESL; forming an opening in the second dielectric layer to expose a portion of the ESL; removing the exposed portion of the ESL; removing the sacrificial semiconductor material; and forming a conductive material in the openings to form an interconnect structure.

## Claims

### Claim 1

A method comprising:
forming a first dielectric layer above a substrate;
forming a via opening in the first dielectric layer;
filling the via opening with a sacrificial semiconductor material;
forming a first layer on the first dielectric layer and the sacrificial semiconductor material;
forming a second dielectric layer on the first layer;
forming a wire opening in the second dielectric layer to expose a portion of the first layer, the wire opening positioned above the sacrificial semiconductor material in the first dielectric layer;
removing the exposed portion of the first layer to expose an upper surface of the sacrificial semiconductor material;
removing the sacrificial semiconductor material from the via opening; and
forming a conductive material in the via opening and the wire opening to form an interconnect structure.

### Claim 2 (depends on 1)

The method of claim 1, further comprising planarizing the sacrificial semiconductor material and the second dielectric layer before forming the first layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming first dielectric layer includes forming the first dielectric layer above a third dielectric layer positioned on the substrate, the third dielectric layer including a via structure positioned therein.

### Claim 4 (depends on 3)

The method of claim 3, wherein forming the via opening in includes exposing an upper surface of the via structure.

### Claim 5 (depends on 3)

The method of claim 3, further comprising, before forming the first dielectric layer above the third dielectric layer, forming a second layer on the third dielectric layer, wherein forming the first dielectric layer includes forming the first dielectric layer on the second layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein forming the via opening includes exposing and removing a portion of the second layer to expose an upper surface of the via structure.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the wire opening includes forming a hard mask on the second dielectric layer, and etching the wire opening in the second dielectric layer.

### Claim 8 (depends on 7)

The method of claim 7, further comprising removing the hard mask after forming the wire opening.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first layer remains above the sacrificial semiconductor material during the removal of the hard mask.

### Claim 10 (depends on 9)

The method of claim 9, wherein the hard mask includes titanium nitride.

### Claim 11 (depends on 1)

The method of claim 1, wherein the first layer acts as an etch stop during the formation of the wire opening.

### Claim 12 (depends on 1)

The method of claim 1, wherein the first layer includes a low temperature oxide.

### Claim 13

A method of forming an interconnect, the method comprising:
forming a first dielectric layer above a substrate
forming a first via in the first dielectric;
forming a second dielectric layer above the first dielectric layer;
forming a via opening in the second dielectric layer above the first via;
forming a sacrificial semiconductor material in the via opening;
forming a first layer on the second dielectric layer and the sacrificial semiconductor material;
forming a third dielectric layer on the first layer;
forming a wire opening in the third dielectric layer to expose a portion of the first layer, the wire opening positioned above the sacrificial semiconductor material;
removing the exposed portion of the first layer to expose the sacrificial semiconductor material;
removing the sacrificial semiconductor material from the via opening to expose an upper surface of the first via in the first dielectric layer; and
forming a conductive material in the via opening and the wire opening to form the interconnect on the first via, the interconnect including a second via and a first wire.

### Claim 14 (depends on 13)

The method of claim 13, further comprising forming a second layer on the first dielectric layer before forming the second dielectric layer.

### Claim 15 (depends on 14)

The method of claim 14, further comprising removing a portion of the second layer to expose the upper surface of the first via before forming the conductive material in the via opening and the wire opening.

### Claim 16 (depends on 13)

The method of claim 13, wherein the first layer acts as an etch stop during the formation of the wire opening.

### Claim 17 (depends on 13)

The method of claim 13, wherein the first layer includes a low temperature oxide.