# US 10,312,187 B2 · Multi-row wiring member for semiconductor device and method for manufacturing the same

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- Number: US 10,312,187 B2
- Document ID: US10312187B2
- Status: Granted
- Kind: B2
- Application number: 16/196,282
- Filed: 2018-11-20
- Published: 2019-03-21
- Granted: 2019-06-04
- Earliest claimed: 2016-05-20
- Assignees: Ohkuchi Materials Co., Ltd.
- Applicants: Ohkuchi Materials Co., Ltd.
- Inventors: Kaoru Hishiki; Ichinori Iidani
- Web page: https://patentgrep.com/patent/US10312187B2

## CPC

- H10W 70/685: comprising multiple insulating layers
- H05K 1/02: Details
- H05K 1/11: Printed elements for providing electric connections to or between printed circuits
- H05K 1/18: structurally associated with non-printed electric components (H05K1/16 takes precedence)
- H05K 3/00: Apparatus or processes for manufacturing printed circuits
- H05K 3/303: with surface mounted components (H05K3/32 takes precedence)
- H05K 3/40: Forming printed elements for providing electric connections to or between printed circuits
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/0198: {batch processes}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/635: {Through-vias}
- H10W 70/655: Fan-out layouts
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A multi-row wiring member for semiconductor device configured of a plurality of wiring members arrayed in a matrix includes a resin layer, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the resin layer with lower faces thereof uncovered in the bottom surface of the resin layer. The plating layer forming wiring portions is formed on the first plating layer in the resin layer. The second plating layer is formed on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the resin layer. On a bottom-surface side of the resin layer, a resin frame is integrally formed with the resin layer at the margin around an aggregate of individual wiring members for semiconductor devices arrayed in a matrix.

## Claims

### Claim 1

A multi-row wiring member for semiconductor device configured of a plurality of wiring members for semiconductor devices arrayed in a matrix including:
a resin layer;
a first plating layer, which is to become internal terminals, formed in the resin layer with lower faces thereof being uncovered at predetermined sites in a bottom surface of the resin layer;
a plating layer that is to become wiring portions, connected with the first plating layer in the resin layer; and
a second plating layer, which is to become external terminals, formed, in the resin layer on partial areas within areas of the plating layer that is to become wiring portions, with upper faces thereof being uncovered on a top-surface side of the resin layer,
wherein a side view of each laminated piece of plating layers forming one of the internal terminals, one of the wiring portions, and one of the external terminals substantially has an L shape or an inverted T shape, and
wherein, on a bottom-surface side of the resin layer, a resin frame portion is integrally formed with the resin layer at a site that is to be a margin around an aggregate of individual wiring members for semiconductor devices arrayed in a matrix.

### Claim 2 (depends on 1)

The multi-row wiring member for semiconductor device according to claim 1, wherein the plating layer that is to become wiring portions is formed on the first plating layer with plating boundaries thereof coinciding with plating boundaries of the first plating layer.

### Claim 3 (depends on 1)

The multi-row wiring member for semiconductor device according to claim 1,
wherein an upper surface of the plating layer that is to become wiring portions formed on the first plating layer is a roughened surface.

### Claim 4 (depends on 1)

The multi-row wiring member for semiconductor device according to claim 1,
wherein a bottom surface of the resin layer in which the first plating layer is left uncovered is a rough surface.

### Claim 5

A method for manufacturing a multi-row wiring member for semiconductor device configured of a plurality of wiring members for semiconductor devices arrayed in a matrix including:
a step of forming, on a front surface of a metal sheet, a first resist mask having an opening at a site that is to be a margin around an aggregate of wiring members for semiconductor devices arrayed in a matrix;
a step of performing half-etching from a front-surface side of the metal sheet, to form a concavity in a metal surface left uncovered at the opening;
a step of peeling off the first resist mask formed on the front surface of the metal sheet;
a step of forming, on the front surface of the metal sheet, a second resist mask covering the concavity and having pattern-A openings;
a step of forming, in the pattern-A openings, a first plating layer, which is to become internal terminals, and a plating layer that is to become wiring portions, connected with the first plating layer;
a step of peeling off the second resist mask formed on the front surface of the metal sheet;
a step of forming, on a front-surface side of the metal sheet, a third resist mask covering the concavity and having pattern-B openings that leave uncovered partial areas within areas of the plating layer that is to become wiring portions;
a step of forming a second plating layer, which is to become external terminals, in the pattern-B openings;
a step of peeling off the third resist mask formed on the front side of the metal sheet;
a step of forming a resin layer on the metal sheet and the plating layer that is to become wiring portions at sites free from the second plating layer while leaving upper faces of the second plating layer uncovered and filling the concavity; and
a step of removing the metal sheet by etching or peeling.

### Claim 6 (depends on 5)

The method for manufacturing a multi-row wiring member for semiconductor device according to claim 5,
wherein the plating layer that is to become wiring portions is formed on the first plating layer to have plating boundaries coinciding with plating boundaries of the first plating layer.

### Claim 7 (depends on 5)

The method for manufacturing a multi-row wiring member for semiconductor device according to claim 5,
wherein an upper surface of the plating layer that is to become wiring portions undergoes roughening treatment after formation of the plating layer that is to become wiring portions and before formation of the third resist mask or the plating layer that is to become wiring portions is formed as a roughened plating layer.

### Claim 8 (depends on 5)

The method for manufacturing a multi-row wiring member for semiconductor device according to claim 5,
further comprising a step of carrying out roughening treatment of the surface of the metal sheet upon using, as a mask, the plating layer that is to become wiring portions formed on the metal sheet after removal of the first resist mask and the second resist mask formed on the respective surfaces of the metal sheet.