# US 10,312,184 B2 · Semiconductor systems having premolded dual leadframes

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- Number: US 10,312,184 B2
- Document ID: US10312184B2
- Status: Granted
- Kind: B2
- Application number: 14/932,055
- Filed: 2015-11-04
- Published: 2017-05-04
- Granted: 2019-06-04
- Earliest claimed: 2015-11-04
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Rajeev D. Joshi; Hau Nguyen; Anindya Poddar; Ken Pham
- Web page: https://patentgrep.com/patent/US10312184B2

## CPC

- H10W 70/442: {of multiple leadframes in a single chip}
- H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps}
- H10W 70/042: {Etching}
- H10W 70/435: {of insulating layers on leadframes, e.g. bridging members}
- H10W 90/00: Package configurations
- H10W 90/811: {Multiple chips on leadframes}
- H10W 70/433: {of deformation-absorbing parts, e.g. leads having meandering shapes (H10W70/481 takes precedence)}
- H10W 70/457: {of metallic layers on leadframes}
- H10W 70/458: {of insulating layers on leadframes}
- H10W 70/475: {Capacitors in combination with leadframes}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07354: {changes in dispositions}
- H10W 72/074: {of anisotropic conductive adhesives}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

## Claims

### Claim 1

A semiconductor system comprising:
a molded dual leadframe having a surface with coplanar metallic and insulating regions, the dual leadframe including a first leadframe formed below and linked with a second leadframe, the first leadframe including zones of a first metal thickness and zones of a second metal thickness smaller than the first thickness, and the second leadframe including zones of a third metal thickness and zones of a fourth metal thickness smaller than the third thickness;
a first active semiconductor chip flip-attached to metallic regions of the surface; and
a passive electronic component conductively attached to metallic regions of the surface.

### Claim 2 (depends on 1)

The system of claim 1 wherein the dual leadframe includes locations having a space volume formed between a metal zone of second thickness aligned with a metal zone of fourth thickness, the space volume suitable to house a second active semiconductor chip.

### Claim 3 (depends on 2)

The system of claim 2, wherein the first and the second active semiconductor chips are the transistors and integrated circuits of a power supply converter, and the passive component is an inductor roofing over the first chip.

### Claim 4 (depends on 3)

The system of claim 3 wherein the semiconductor chips are made of a material selected from a group including silicon, silicon germanium, gallium nitride, and gallium arsenide.

### Claim 5

A semiconductor system comprising:
a dual leadframe including a first leadframe formed below and linked with a second leadframe, the first leadframe including zones of a first metal thickness and zones of a second metal thickness smaller than the first thickness, and the second leadframe including zones of a third metal thickness and a fourth metal thickness smaller than the third thickness; the dual leadframe having no electronic devices located between the first leadframe and the second leadframe; and
at least one semiconductor chip attached to the top surface of the dual leadframe.

### Claim 6 (depends on 5)

The system of claim 5 further including at least one passive electronic component attached to the top surface of the dual leadframe.

### Claim 7 (depends on 6)

The system of claim 6 further including a molded package encapsulating the dual leadframe with the at least one semiconductor chip attached.

### Claim 8

A semiconductor system comprising:
a dual leadframe including a first leadframe formed below and linked with a second leadframe, the first leadframe including zones of a first metal thickness and zones of a second metal thickness smaller than the first thickness, and the second leadframe including zones of a third metal thickness and a fourth metal thickness smaller than the third thickness;
at least one semiconductor chip attached to the top surface of the dual leadframe; and
locations of the dual leadframe where metal zones of second thickness are aligned with metal zones of fourth thickness, the locations forming spaces suitable for housing electronic components.

### Claim 9 (depends on 8)

The system of claim 8 wherein at least one of the spaces has a semiconductor chip attached to the dual leadframe, embedding the chip inside the dual leadframe before encapsulating the dual leadframe.

### Claim 10 (depends on 5)

The system of claim 5 wherein the semiconductor chips are made of a material selected from a group including silicon, silicon germanium, gallium nitride, and gallium arsenide.

### Claim 11

A semiconductor system, comprising:
a first leadframe having zones of a first thickness and a second thickness and having at least one first joint location;
a second leadframe formed over the first leadframe, the second leadframe having zones of a third thickness and a fourth thickness and having at least one second joint location;
an electrical connection formed by the at least one first joint location contacting the at least one second joint location; and
a semiconductor device electrically connected to at least one of the first and second leadframes.

### Claim 12 (depends on 11)

The system of claim 11, comprising at least one passive electronic component electrically connected to at least one of the first and second leadframes.

### Claim 13 (depends on 11)

The system of claim 11, comprising a molded package encapsulating the first and second leadframes.

### Claim 14 (depends on 11)

The system of claim 11, wherein a zone of the second thickness is aligned with a zone of fourth thickness to form a space for the semiconductor device.

### Claim 15 (depends on 14)

The system of claim 14, wherein the semiconductor device is electrically connected to at least one of the first and second leadframes between a lower surface of the first leadframe and an upper surface of the second leadframe.

### Claim 16 (depends on 11)

The system of claim 11, wherein the semiconductor device is electrically connected to an upper surface of the second leadframe.

### Claim 17 (depends on 11)

The system of claim 11, wherein the electrical connection formed between the at least one first joint location and the at least one second joint location comprises solder alloy.

### Claim 18 (depends on 11)

The system of claim 11, wherein the electrical connection formed between the at least one first joint location and the at least one second joint location comprises metal plating.

### Claim 19 (depends on 11)

The system of claim 11, wherein the electrical connection between the semiconductor device and the at least one of the first and second leadframes comprises flip-chip bonding.

### Claim 20 (depends on 11)

The system of claim 11, wherein the second thickness is less than the first thickness, and wherein the fourth thickness is less than the third thickness, and wherein the second and fourth thicknesses are formed by a half-etch process.