# US 10,312,182 B2 · Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,312,182 B2
- Document ID: US10312182B2
- Status: Granted
- Kind: B2
- Application number: 16/154,711
- Filed: 2018-10-08
- Published: 2019-02-07
- Granted: 2019-06-04
- Earliest claimed: 2005-06-08
- Assignees: Advanced Interconnect Systems Limited
- Applicants: Advanced Interconnect Systems Limited
- Inventors: Haruki Ito; Nobuaki Hashimoto
- Web page: https://patentgrep.com/patent/US10312182B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H03H 9/0547: {consisting of a vertical arrangement (H03H9/0566 takes precedence)}
- H03H 9/0552: {the device and the other elements being mounted on opposite sides of a common substrate}
- H03H 9/1071: {the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes}
- H10W 72/00: Interconnections or connectors in packages
- H10W 70/655: Fan-out layouts
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)

## Abstract

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

## Claims

### Claim 1

A device comprising:
a semiconductor substrate including a first face and a second face on a side opposite to the first face;
a first electrode formed on the first face of the semiconductor substrate;
a second electrode formed on the first face of the semiconductor substrate;
an integrated circuit comprising at least two interconnected semiconductor devices, the at least two interconnected semiconductor devices formed on the first face, and the integrated circuit being electrically connected to the first electrode and the second electrode;
a rear face electrode formed on the second face of the semiconductor substrate;
a groove portion formed in the semiconductor substrate, the groove portion having an inner wall;
an insulating film formed on side walls of the groove portion;
a conductive portion formed inside the groove portion on the insulating portion and electrically connected to the second electrode and the rear face electrode;
a second semiconductor substrate including a second semiconductor substrate first face and a second semiconductor substrate second face on a side opposite to the second semiconductor first face; and
an electronic element formed on the first face of the second semiconductor substrate, the electronic element being electrically connected to the rear face electrode;
wherein the integrated circuit is configured to apply a voltage to the electronic element via the second electrode and conductive portion; and
wherein the first electrode, the integrated circuit, the second electrode, the conductive portion, the rear face electrode and the electronic element are electrically connected in that order.

### Claim 2 (depends on 1)

The device of claim 1, wherein the semiconductor substrate is silicon.

### Claim 3 (depends on 2)

The device of claim 2, wherein:
the second electrode comprises a second electrode rear face facing the first face of the semiconductor substrate;
the rear face electrode comprises a rear face electrode bottom face facing the second face of the semiconductor substrate; and
a first end of the conductive portion is electrically connected to the rear face of the second electrode and a second end of the conductive portion is electrically connected to the rear face electrode.

### Claim 4 (depends on 2)

The device of claim 2, wherein the conductive portion and rear face electrode are integrally formed.

### Claim 5 (depends on 2)

The device of claim 2,
wherein the second semiconductor substrate first face is facing the second face of the semiconductor substrate.

### Claim 6 (depends on 2)

The device of claim 2, wherein the second semiconductor substrate is silicon.

### Claim 7 (depends on 2)

The device of claim 2, further comprising:
an external connection terminal formed on the first face of the semiconductor substrate; and
an interconnection section formed on the first face, the interconnection section being electrically connected to the first electrode and to the external connection terminal;
wherein the interconnection section is electrically disposed between the first electrode and the external connection terminal.

### Claim 8 (depends on 7)

The device of claim 7, wherein the interconnection section is in a different layer than the first electrode.

### Claim 9 (depends on 8)

The device of claim 8, wherein:
the interconnection section further comprises an interconnection horizontal section and an interconnection vertical section;
the interconnection horizontal section is electrically connected to the external connection terminal;
the interconnection vertical section is electrically connected to the first electrode and to the interconnection horizontal section;
the interconnection horizontal section is in a different layer than the first electrode; and
the interconnection vertical section traverses the one more layers between the interconnection horizontal section and the first electrode.

### Claim 10 (depends on 2)

The device of claim 2, wherein the integrated circuit comprises a memory element.

### Claim 11 (depends on 2)

The device of claim 2, further comprising:
an insulating layer formed on the first face;
wherein the insulating layer is disposed in a layer between the second electrode and the external connection terminal.

### Claim 12 (depends on 2)

The device of claim 2, wherein the first electrode is displaced from the second electrode in plan view.

### Claim 13 (depends on 2)

The device of claim 2, further comprising:
an external connection terminal formed on the first face of the semiconductor substrate, the external connection terminal being electrically connected to the first electrode;
wherein the second electrode is displaced from the external connection terminal in plan view; and
wherein the external connection terminal, first electrode, the integrated circuit, the second electrode, the conductive portion, the rear face electrode and the electronic element are electrically connected in that order.

### Claim 14

A device comprising:
a semiconductor substrate including a first face and a second face on a side opposite to the first face;
an external connection terminal formed on the first face of the semiconductor substrate;
a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal;
a second electrode formed on the first face of the semiconductor substrate;
an integrated circuit comprising at least two interconnected semiconductor devices, the at least two interconnected semiconductor devices formed on the first face, and the integrated circuit being electrically connected to the first electrode and the second electrode;
a rear face electrode formed on the second face of the semiconductor substrate;
an electronic element formed above the second face of the semiconductor substrate, the electronic element being electrically connected to the rear face electrode;
a groove portion formed in the semiconductor substrate, the groove portion having an inner wall;
an insulating film formed on side walls of the groove portion; and
a conductive portion formed inside the groove portion on the insulating portion and electrically connected to the second electrode and the rear face electrode;
wherein the external connection terminal, first electrode, the integrated circuit, the second electrode, the conductive portion, the rear face electrode and the electronic element are electrically connected in that order.

### Claim 15 (depends on 14)

The device of claim 14, further comprising:
a second semiconductor substrate including a second semiconductor substrate first face and a second semiconductor substrate second face on a side opposite to the second semiconductor first face; and
a second semiconductor substrate terminal formed on the second semiconductor first face, the second semiconductor substrate terminal being electrically connected to the rear face electrode and to the electronic element;
wherein:
the electronic element is formed on the first face of the second semiconductor substrate;
the second semiconductor substrate terminal is electrically disposed between the rear face electrode and the electronic element;
the second semiconductor substrate first face is facing the second face of the semiconductor substrate; and
the second semiconductor substrate is silicon.

### Claim 16 (depends on 15)

The device of claim 15, further comprising:
an interconnection section formed on the first face, the interconnection section being electrically connected to the first electrode and to the external connection terminal;
wherein the interconnection section is electrically disposed between the first electrode and the external connection terminal.

### Claim 17 (depends on 16)

The device of claim 16, wherein the interconnection section is in a different layer than the first electrode.

### Claim 18 (depends on 17)

The device of claim 17, wherein:
the interconnection section further comprises an interconnection horizontal section and an interconnection vertical section;
the interconnection horizontal section is electrically connected to the external connection terminal;
the interconnection vertical section is electrically connected to the first electrode and to the interconnection horizontal section;
the interconnection horizontal section is in a different layer than the first electrode; and
the interconnection vertical section traverses the one more layers between the interconnection horizontal section and the first electrode.

### Claim 19 (depends on 15)

The device of claim 15, wherein the integrated circuit comprises a memory element.

### Claim 20 (depends on 15)

The device of claim 15, further comprising:
an insulating layer formed on the first face;
wherein the insulating layer is disposed in a layer between the second electrode and the external connection terminal.

### Claim 21 (depends on 15)

The device of claim 15, wherein the first electrode is displaced from the second electrode in plan view.

### Claim 22 (depends on 15)

The device of claim 15, wherein the second electrode is displaced from the external connection terminal in plan view.

### Claim 23 (depends on 15)

The device of claim 15, wherein the integrated circuit drives the electronic element.

### Claim 24 (depends on 15)

The device of claim 15, wherein the integrated circuit controls the electronic element.

### Claim 25

A device comprising:
a semiconductor substrate including a first face and a second face on a side opposite to the first face;
an external connection terminal formed on the first face of the semiconductor substrate;
a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal;
a second electrode formed on the first face of the semiconductor substrate;
an integrated circuit comprising at least two interconnected semiconductor devices, the at least two interconnected semiconductor devices formed on the first face, and the integrated circuit being electrically connected to the first electrode and the second electrode;
an electronic element formed on the second face of the semiconductor substrate;
a groove portion formed in the semiconductor substrate, the groove portion having an inner wall;
an insulating film formed on side walls of the groove portion; and
a conductive portion formed inside the groove portion on the insulating portion and electrically connected to the second electrode and the electronic element;
wherein the external connection terminal, first electrode, the integrated circuit, the second electrode, the conductive portion, the rear face electrode and the electronic element are electrically connected in that order; and
wherein the semiconductor substrate is silicon.

### Claim 26 (depends on 25)

The device of claim 25, further comprising:
an interconnection section formed on the first face, the interconnection section being electrically connected to the first electrode and to the external connection terminal;
wherein the interconnection section is electrically disposed between the first electrode and the external connection terminal.

### Claim 27 (depends on 25)

The device of claim 25, wherein the first electrode is displaced from the second electrode in plan view.

### Claim 28 (depends on 25)

The device of claim 25, wherein the integrated circuit drives the electronic element.

### Claim 29 (depends on 25)

The device of claim 25, wherein the integrated circuit controls the electronic element.