# US 10,312,178 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,178 B2 - Document ID: US10312178B2 - Status: Granted - Kind: B2 - Application number: 15/541,507 - Filed: 2015-04-15 - Published: 2018-01-04 - Granted: 2019-06-04 - Earliest claimed: 2015-04-15 - Assignees: Mitsubishi Electric Corporation - Applicants: Mitsubishi Electric Corporation - Inventors: Takanobu Kajihara; Katsuhiko Omae; Shunsuke Fushie; Muneaki Mukuda; Daisuke Nakashima; Masahiro Motooka; Hiroyuki Miyanishi; Yuki Nakamatsu; Junya Suzuki - Web page: https://patentgrep.com/patent/US10312178B2 ## CPC - H10W 40/778: {in encapsulations} - H10W 40/10: Arrangements for heating - H10W 70/466: {Tape carriers or flat leads} - H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 74/016: {using moulds} - H10W 74/10: characterised by their shape or disposition - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 74/127: {characterised by arrangements for sealing or adhesion} - H10W 74/40: characterised by their materials - H10W 90/00: Package configurations - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/475: {Capacitors in combination with leadframes} - H10W 72/652: {comprising metals or metalloids, e.g. silver} - H10W 72/655: {of outermost layers of multilayered strap connectors, e.g. material of a coating} - H10W 72/871: {Bond wires and strap connectors} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract In a semiconductor device, a thinly-molded portion covering a whole of a heat dissipating surface portion of a lead frame and a die pad space filled portion are integrally molded from a second mold resin, because of which adhesion between the thinly-molded portion and lead frame improves owing to the die pad space filled portion adhering to a side surface of the lead frame. Also, as the thinly-molded portion is partially thicker owing to the die pad space filled portion, strength of the thinly-molded portion increases, and a deficiency or cracking is unlikely to occur. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor element mounted in a mounting portion of a lead frame; a first mold resin that seals the mounting portion; and a second mold resin that seals a heat dissipating portion of the lead frame opposing the mounting portion, wherein the second mold resin comprises a thinly-molded portion covering the heat dissipating portion of the lead frame, and a lead frame space filled portion disposed in at least one portion of internal open regions between two separate regions of the lead frame distant from an outer edge of the lead frame, where the thinly molded portion and the lead frame space filled portion are integrally molded from the second mold resin, and at least one portion of the internal open region is filled with the first mold resin, and the first mold resin filling the internal open region has a depressed portion in an interface with the second mold resin. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the second mold resin has a gate break mark, which is a trace of resin remaining in a gate of a molding die used in a transfer molding step, and the lead frame space filled portion is disposed adjacent to the gate break mark. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein there is burr on one portion of a side surface of the lead frame in which the lead frame space filled portion is disposed. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein a roughened metal plating lead frame coated with a metal plating, whose surface is roughened to surface roughness Ra having a value of 0.06 to 0.2, is used as the lead frame. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the lead frame is covered with a metal plating, and has a scale form portion that causes a surface form of the metal plating to change into a scale form. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the first mold resin has a gate break mark, which is a trace of resin remaining in a gate of a molding die used in a transfer molding step, and the scale form portion is disposed in a place adjacent to the gate break mark of the mounting portion of the lead frame. ### Claim 7 (depends on 5) The semiconductor device according to claim 5, wherein the second mold resin has the gate break mark, which is a trace of resin remaining in the gate of the molding die used in a transfer molding step, and the scale form portion is disposed in a place adjacent to the gate break mark of the heat dissipating portion of the lead frame. ### Claim 8 (depends on 5) The semiconductor device according to claim 5, wherein the scale form portion is disposed in an outer peripheral portion of either or both of the mounting portion and heat dissipating portion of the lead frame. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein a high-heat dissipating resin with a thermal conductivity higher than that of the first mold resin is used for the second mold resin. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein a high-heat dissipating resin with a thermal conductivity of 3 W/m·K to 12 W/m·K is used for the first mold resin and second mold resin. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the second mold resin includes a filler with a maximum diameter of 0.02 mm to 0.15 mm, and a thickness of the thinly-molded portion is 0.022 mm to 0.3 mm. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein a heatsink is joined directly to the thinly-molded portion covering the heat dissipating portion of the lead frame. ### Claim 13 A semiconductor device, comprising: a semiconductor element mounted in a mounting portion of a lead frame; a first mold resin that seals the mounting portion; a second mold resin that seals a heat dissipating portion of the lead frame opposing the mounting portion; and an electronic part bridge-mounted on the mounting portion so as to straddle two separate regions of the lead frame, wherein a depression is provided in the second mold resin corresponding to a position directly below the electronic part, the depression is filled with the first mold resin, and the second mold resin comprises a thinly-molded portion covering the heat dissipating portion of the lead frame and a lead frame space filled portion disposed in at least one portion between two separate regions of the lead frame, where the thinly molded portion and the lead frame space filled portion are integrally molded from the second mold resin.