# US 10,312,171 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,171 B2 - Document ID: US10312171B2 - Status: Granted - Kind: B2 - Application number: 15/827,946 - Filed: 2017-11-30 - Published: 2018-04-05 - Granted: 2019-06-04 - Earliest claimed: 2013-04-16 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Kensuke Mikado; Makoto Shibuya; Yasufumi Matsuoka - Web page: https://patentgrep.com/patent/US10312171B2 ## CPC - H10W 74/47: comprising organic materials, e.g. plastics or resins - H10W 70/20: Conductive package substrates serving as an interconnection, e.g. metal plates (leadframes H10W70/40) - H10W 70/411: {Chip-supporting parts, e.g. die pads} - H10W 70/415: {Leadframe inner leads serving as die pads} - H10W 70/417: {Bonding materials between chips and die pads} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/465: {Bumps or wires} - H10W 70/466: {Tape carriers or flat leads} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 74/147: {the encapsulations being multilayered} - H10W 72/07141: {Means for applying energy, e.g. ovens or lasers} - H10W 72/07511: {Treating the bonding area before connecting, e.g. by applying flux or cleaning} - H10W 72/07521: {Aligning} - H10W 72/522: {Multilayered bond wires, e.g. having a coating concentric around a core} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/5434: {the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5522: {comprising gold [Au]} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor element provided with a first electrode and a second electrode; a main lead on which the semiconductor element is disposed; a first sublead facing the main lead; a first wire having a first end and a second end that are connected to the first electrode and the first sublead, respectively; a second wire having a first end and a second end, the first end of the second wire being connected to the second electrode, the second wire being disposed on a left side of the first wire as viewed in a thickness direction of the semiconductor element as proceeding along the first wire from the first electrode toward the first sublead; a resin package covering the semiconductor element, the main lead, the first sublead, the first wire and the second wire, the resin package having a rectangular shape as viewed in the thickness direction of the semiconductor element, wherein the resin package has a first surface and a second surface, the first surface having a normal direction parallel to the thickness direction, the second surface having a normal direction perpendicular to the thickness direction, the main lead and the first sublead are exposed from the first surface of the resin package, the main lead and the first sublead have a first portion and a second portion, respectively, that are exposed from the second surface of the resin package, as viewed in the thickness direction of the semiconductor element, the first end of the second wire is offset toward the first sublead with respect to the first end of the first wire in a first direction parallel to the second surface of the resin package. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the main lead comprises a first side projection and a second side projection that extend mutually opposite in a second direction perpendicular to the first direction as viewed in the thickness direction of the semiconductor element, the first end of the first wire is aligned with the first side projection and the second side projection along the second direction. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the main lead comprises a first rear projection and a second rear projection that are disposed on a side opposite to the first sublead and spaced apart from each other in the second direction, the first end of the first wire and the first end of the second wire are each disposed between the first rear projection and the second rear projection in the second direction. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor element includes a part that does not overlap with the main lead as viewed in the thickness direction. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the main lead has a main-lead obverse surface and a main-lead reverse surface, the semiconductor element is disposed on the main-lead obverse surface, and the main-lead reverse surface is exposed from the first surface of the resin package. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the main lead includes a main-lead full-thickness portion and a main-lead eaved portion, the main-lead full-thickness portion extending from the main-lead obverse surface to the main-lead reverse surface, the main-lead eaved portion projecting from the main-lead full-thickness portion so as to cross the thickness direction. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the first electrode overlaps with both the main-lead full-thickness portion and the main-lead eaved portion as viewed in the thickness direction. ### Claim 8 (depends on 6) The semiconductor device according to claim 6, wherein an entirety of the semiconductor element overlaps with the main-lead full-thickness portion as viewed in the thickness direction. ### Claim 9 (depends on 6) The semiconductor device according to claim 6, wherein the main-lead eaved portion includes a main-lead front portion projecting from the main-lead full-thickness portion toward the first sublead. ### Claim 10 (depends on 6) The semiconductor device according to claim 6, wherein an entirety of the main-lead full-thickness portion is surrounded by the main-lead eaved portion as viewed in the thickness direction. ### Claim 11 (depends on 6) The semiconductor device according to claim 6, wherein an entirety of the main-lead eaved portion overlaps with the semiconductor element as viewed in the thickness direction. ### Claim 12 (depends on 6) The semiconductor device according to claim 6, further comprising a main-lead obverse surface plating layer disposed between the semiconductor element and the main lead. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the main-lead obverse surface plating layer overlaps with an entirety of the main-lead eaved portion. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the first sublead has a first sublead obverse surface and a first sublead reverse surface that is exposed from the resin package, the first sublead includes a first sublead full-thickness portion and a first sublead eaved portion, the first sublead full-thickness portion extending from the first sublead obverse surface to the first sublead reverse surface, the first sublead eaved portion projecting from the first sublead full-thickness portion so as to cross the thickness direction, the first sublead eaved portion forming a part of the first sublead obverse surface. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the first sublead eaved portion includes a first sublead front portion projecting from the first sublead full-thickness portion toward the main lead. ### Claim 16 (depends on 14) The semiconductor device according to claim 14, wherein the first sublead includes a first sublead extension that extends from the first sublead full-thickness so as to cross the thickness direction, and that forms the first sublead reverse surface, the first sublead extension has an end surface parallel to the thickness direction and exposed from the resin package. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, wherein the first sublead has a first sublead obverse surface and a first sublead reverse surface, and the first sublead reverse surface is exposed from the first surface of the resin package. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, wherein the first sublead reverse surface is flush with the first surface of the resin package. ### Claim 19 (depends on 17) The semiconductor device according to claim 17, wherein the first sublead includes a first sublead end surface connected to the first sublead reverse surface, and the first sublead end surface faces away from the main lead. ### Claim 20 (depends on 19) The semiconductor device according to claim 19, wherein the first sublead end surface is exposed from the resin package. ### Claim 21 (depends on 19) The semiconductor device according to claim 19, wherein the resin package has a resin end surface that is flush with the first sublead end surface. ### Claim 22 (depends on 19) The semiconductor device according to claim 19, wherein the second portion of the first sublead includes a first sublead side surface connected to the first sublead reverse surface, and the first sublead side surface faces in a direction perpendicular to both the direction in which the first sublead end surface faces and the thickness direction of the semiconductor element. ### Claim 23 (depends on 22) The semiconductor device according to claim 22, wherein the first sublead side surface is exposed from the resin package. ### Claim 24 (depends on 22) The semiconductor device according to claim 22, wherein the resin package has a resin side surface that is flush with the first sublead side surface. ### Claim 25 (depends on 1) The semiconductor device according to claim 1, further comprising a first sublead plating layer disposed between the first sublead and the first wire. ### Claim 26 (depends on 1) The semiconductor device according to claim 1, further comprising a second sublead electrically connected to the semiconductor element via the second wire and covered with the resin package, wherein the second sublead is spaced apart from the main lead and the first sublead and has a portion exposed from the resin package. ### Claim 27 (depends on 26) The semiconductor device according to claim 26, further comprising a second sublead plating layer disposed between the second sublead and the second wire. ### Claim 28 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor element comprises a semiconductor layer, a eutectic layer of semiconductor and metal, and a single metal layer, and the single metal layer is attached to the main lead. ### Claim 29 (depends on 28) The semiconductor device according to claim 28, wherein the eutectic layer is made of Si and Au. ### Claim 30 (depends on 29) The semiconductor device according to claim 29, wherein the single metal layer is thinner than the the eutectic layer. ### Claim 31 (depends on 1) The semiconductor device according to claim 1, wherein the main lead has a third portion exposed from the first surface and the first sublead has a fourth portion exposed from the first surface, wherein the third portion is on a first side relative to a central line of the first surface, and the fourth portion is on a second side relative to the central line of the first surface, and wherein the third portion and the fourth portion are different from each other in area measured in the first surface. ### Claim 32 (depends on 1) The semiconductor device according to claim 1, wherein the first portion and the second portion, respectively, have a first edge and a second edge that are perpendicular to the thickness direction, and the first edge and the second edge are in a same line.