# US 10,312,167 B2 · Semiconductor package, assembly and module arrangements for measuring gate-to-emitter/source voltage

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- Number: US 10,312,167 B2
- Document ID: US10312167B2
- Status: Granted
- Kind: B2
- Application number: 15/433,706
- Filed: 2017-02-15
- Published: 2018-08-16
- Granted: 2019-06-04
- Earliest claimed: 2017-02-15
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Reinhold Bayerer
- Web page: https://patentgrep.com/patent/US10312167B2

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10D 1/47: Resistors having no potential barriers
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/00: Package configurations
- H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M 7/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections}
- H10W 44/216: {Waveguides, e.g. strip lines}
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/527: {Multiple bond wires having different sizes}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 72/652: {comprising metals or metalloids, e.g. silver}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

One or more additional sense terminals are added to discrete semiconductor packages, assemblies and semiconductor modules, including power semiconductor modules, to sense accurately the voltage between the gate and emitter/source of voltage-controlled chips, inside the package, assembly or module.

## Claims

### Claim 1

A semiconductor package, comprising:
a single controllable power semiconductor die embedded in a molding compound, the power semiconductor die comprising a gate pad, an emitter/source pad and a collector/drain pad;
a first terminal protruding from the molding compound and electrically connected to the gate pad of the power semiconductor die;
a second terminal protruding from the molding compound and electrically connected to an additional gate pad of the power semiconductor die;
a third terminal protruding from the molding compound and electrically connected to the collector/drain pad of the power semiconductor die;
a fourth terminal protruding from the molding compound and electrically connected to the emitter/source pad of the power semiconductor die; and
a fifth terminal protruding from the molding compound and electrically connected to the emitter/source pad of the power semiconductor die,
wherein the second terminal and the fourth terminal are configured to carry just a current which is necessary to sense a gate-to-emitter/source voltage of the power semiconductor die,
wherein the power semiconductor die comprises an integrated gate resistor in series with a gate of a power transistor,
wherein the additional gate pad is electrically connected to a node between the gate of the power transistor and the integrated gate resistor.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the single controllable power semiconductor die is an IGBT, MOSFET or HEMT die.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the molding compound is an elastomer, a composite compound, a thermoplastic, a thermoset plastic or a thermosetting plastic.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the single controllable power semiconductor die is a vertical transistor device.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the single controllable power semiconductor die is a lateral transistor device.