# US 10,312,163 B2 · Method of improving surface smoothness of dummy gate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,163 B2 - Document ID: US10312163B2 - Status: Granted - Kind: B2 - Application number: 15/995,283 - Filed: 2018-06-01 - Published: 2019-03-07 - Granted: 2019-06-04 - Earliest claimed: 2017-09-01 - Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation - Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation - Inventors: Hai Yang Zhang; Yan Wang - Web page: https://patentgrep.com/patent/US10312163B2 ## CPC - H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects} - H10D 64/011: {of electrodes ohmically coupled to a semiconductor} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10P 50/268: {of silicon-containing layers} - H10P 52/403: {of conductive or resistive materials} - H10P 72/72: using electrostatic chucks - H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes} - H10P 95/04: {Planarisation of conductive or resistive materials} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present disclosure relates to the field of semiconductor technologies, and discloses a method for manufacturing a semiconductor apparatus. An implementation of the method may include: providing a substrate structure; depositing a dummy gate material layer on the substrate structure; performing planarization processing on the dummy gate material layer; after the planarization processing, performing, according to surface roughness of the dummy gate material layer, first etching on the dummy gate material layer by using a fluorine-containing gas; after the first etching, forming a fluorine-containing polymer layer on the dummy gate material layer; and performing second etching on the substrate structure on which the fluorine-containing polymer layer is formed, to remove the fluorine-containing polymer layer, where the second etching includes etching a surface of the dummy gate material layer. The method of the present invention improves surface smoothness and thickness uniformity of the dummy gate material layer. ## Claims ### Claim 1 A method for manufacturing a semiconductor apparatus, comprising: providing a substrate structure; depositing a dummy gate material layer on the substrate structure; performing planarization processing on the dummy gate material layer; after the planarization processing, performing, according to surface roughness of the dummy gate material layer, first etching on the dummy gate material layer using a fluorine-containing gas; after the first etching, forming a fluorine-containing polymer layer on the dummy gate material layer; and performing second etching on the substrate structure on which the fluorine-containing polymer layer is formed, to remove the fluorine-containing polymer layer, wherein the second etching comprises etching a surface of the dummy gate material layer. ### Claim 2 (depends on 1) The method according to claim 1, wherein the step of performing, according to surface roughness of the dummy gate material layer, first etching on the dummy gate material layer using a fluorine-containing gas comprises: detecting a raised portion and a recessed portion of the dummy gate material layer surface, to obtain the surface roughness of the dummy gate material layer; placing the substrate structure on an electro-static chuck (ESC), and setting a temperature of each region of the ESC according to the surface roughness of the dummy gate material layer, wherein in the ESC, a temperature of a region corresponding to the raised portion is higher than a temperature of a region corresponding to the recessed portion; and performing first etching on the dummy gate material layer using a fluorine-containing gas. ### Claim 3 (depends on 2) The method according to claim 2, wherein the step of performing first etching on the dummy gate material layer using a fluorine-containing gas comprises: in a reaction chamber, under conditions of an atmospheric pressure ranging from 5 to 200 millitorrs (mTorr), an operating power of an etching device ranging from 100 to 1000 watts, and a bias voltage ranging from 0 to 300 volts, performing first etching on the dummy gate material layer using a fluorine-containing gas. ### Claim 4 (depends on 1) The method according to any one of claim 1, wherein the fluorine-containing gas comprises CH4F6, CH2F2, or NF3. ### Claim 5 (depends on 1) The method according to claim 1, wherein in the step of performing second etching, an etching rate of the second etching for the fluorine-containing polymer layer is substantially equal to an etching rate for the dummy gate material layer. ### Claim 6 (depends on 1) The method according to claim 1, wherein the step of forming a fluorine-containing polymer layer on the dummy gate material layer comprises: depositing a fluorine-containing polymer layer on the dummy gate material layer using a gas mixture containing CH3F and Cl2 and using an inert gas as a carrier gas under a condition of a zero-bias voltage. ### Claim 7 (depends on 6) The method according to claim 6, wherein a material of the fluorine-containing polymer layer comprises a carbon-hydrogen-fluorine polymer. ### Claim 8 (depends on 1) The method according to claim 1, wherein the second etching is performed using CF4 or CH2F2 as an etching gas. ### Claim 9 (depends on 8) The method according to claim 8, wherein the step of performing the second etching using CF4 as an etching gas comprises: in a reaction chamber, under conditions of an atmospheric pressure ranging from 10 to 200 mTorr, an operating power of an etching device ranging from 50 to 1000 watts, and a gas flow rate of CF4 ranging from 10 to 500 sccm, performing the second etching; or, the step of performing the second etching using CH2F2 as an etching gas comprises: in a reaction chamber, under conditions of an atmospheric pressure ranging from 10 to 200 mTorr, an operating power of an etching device ranging from 50 to 1000 watts, and a gas flow rate of CH2F2 ranging from 2 to 100 sccm, performing the second etching. ### Claim 10 (depends on 1) The method according to claim 1, further comprising: cyclically performing the step of forming a fluorine-containing polymer layer and the step of performing second etching multiple times. ### Claim 11 (depends on 1) The method according to claim 1, wherein the method further comprises: after performing the second etching, performing ashing processing. ### Claim 12 (depends on 1) The method according to claim 1, wherein a material of the dummy gate material layer comprises polysilicon or amorphous silicon. ### Claim 13 (depends on 1) The method according to claim 1, wherein in the step of providing a substrate structure, the substrate structure comprises: a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a trench separation portion surrounding the semiconductor fin, and a dummy gate insulator layer on a surface of the semiconductor fin; and in the step of depositing a dummy gate material layer on the substrate structure, the dummy gate material layer covers the trench separation portion and the dummy gate insulator layer.