# US 10,312,160 B2 · Gate-last semiconductor fabrication with negative-tone resolution enhancement

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- Number: US 10,312,160 B2
- Document ID: US10312160B2
- Status: Granted
- Kind: B2
- Application number: 15/606,927
- Filed: 2017-05-26
- Published: 2018-11-29
- Granted: 2019-06-04
- Earliest claimed: 2017-05-26
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Effendi Leobandung
- Web page: https://patentgrep.com/patent/US10312160B2

## CPC

- H10D 86/011: {comprising FinFETs}
- H10D 62/82: Heterojunctions
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 86/215: {comprising FinFETs}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of fabricating a transistor includes: forming an active device layer on a semiconductor substrate; patterning the active device layer to form fins; forming a first dielectric layer on an upper surface and sidewalls of the fins; forming a second dielectric layer on the first dielectric layer; forming openings through the first and second dielectric layers, exposing the underlying active device layer forming the fins; forming source/drain regions in the active device layer exposed through the respective openings; forming source/drain contacts on an upper surface of the source/drain regions; forming a second opening through the first and second dielectric layers, exposing the underlying active device layer adjacent to the source/drain regions; depositing a third dielectric layer in the second opening, on sidewalls and an upper surface of the fins; and forming a gate stack on the third dielectric layer.

## Claims

### Claim 1

A method of fabricating a transistor structure, the method comprising:
forming an active device layer on a semiconductor substrate;
patterning the active device layer to form a plurality of fins;
forming a first dielectric layer on at least a portion of an upper surface and sidewalls of the plurality of fins;
forming a second dielectric layer on at least a portion of an upper surface of the first dielectric layer;
forming a first plurality of openings through the second dielectric layer and the first dielectric layer, exposing the underlying active device layer forming the plurality of fins;
forming a plurality of source/drain regions in the active device layer exposed through the respective first plurality of openings;
forming a plurality of source/drain contacts on an upper surface of each of the plurality of source/drain regions;
forming a second opening through the second dielectric layer and the first dielectric layer, the second opening exposing the underlying active device layer adjacent to the plurality of source/drain regions;
depositing a third dielectric layer in at least a portion of the second opening, including on sidewalls of the second opening and sidewalls and an upper surface of the plurality of fins;
patterning a trench, the trench configured for forming a gate; and
forming the gate on the third dielectric layer using the patterned trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein the gate is formed subsequent to the formation of the source/drain regions, the gate being self-aligned with the plurality of source/drain regions.

### Claim 3 (depends on 1)

The method of claim 1, further comprising forming dielectric spacers on sidewalls of the first plurality of openings prior to forming the plurality of source/drain regions.

### Claim 4 (depends on 1)

The method of claim 1, wherein the third dielectric layer comprises a high dielectric constant material and forms an insulating barrier lining openings between adjacent source/drain contacts.

### Claim 5 (depends on 4)

The method of claim 4, wherein the third dielectric layer comprises at least one of hafnium oxide (HfO), zirconium oxide (ZrO), and aluminum oxide (Al2O3).

### Claim 6 (depends on 1)

The method of claim 1, wherein the third dielectric layer is formed having a cross-sectional thickness of about one to three nanometers (nm).

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the gate comprises:
depositing a conductive material having a prescribed work function associated therewith in the second opening on an upper surface of the third dielectric layer; and
depositing a hard mask layer on an upper surface of the conductive material.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first plurality of openings are oriented in a direction substantially perpendicular to a major axis direction of the plurality of fins.

### Claim 9 (depends on 1)

The method of claim 1, wherein each of at least a subset of the source/drain regions comprises a Group III-V material.

### Claim 10 (depends on 9)

The method of claim 9, wherein the Group III-V material comprises at least one of indium gallium arsenide (InGaAs), gallium arsenide (GaAs) and indium phosphide (InP).

### Claim 11 (depends on 1)

The method of claim 1, wherein forming the source/drain regions comprises doping the source/drain regions during epitaxial deposition by adding at least one impurity to a source gas, a type and amount of the at least one impurity being varied as a function of a desired conductivity type and impurity concentration, respectively, of the source/drain regions.

### Claim 12 (depends on 1)

The method of claim 1, wherein the substrate is a silicon-on-insulator (SOI) substrate comprising a carrier substrate, an insulating layer formed on at least a portion of an upper surface of the carrier substrate, and the active device layer formed on at least a portion of an upper surface of the insulating layer.

### Claim 13 (depends on 1)

The method of claim 1, wherein a vertical height of at least a subset of the plurality of fins above an upper surface of the substrate is about 30 nanometers.

### Claim 14 (depends on 1)

The method of claim 1, wherein the source/drain regions are formed in at least a portion of the first plurality of openings covering the plurality of fins by an epitaxial growth process.

### Claim 15 (depends on 14)

The method of claim 14, wherein the epitaxial growth process comprises at least one of chemical vapor deposition, molecular beam epitaxy, and metal organic chemical vapor deposition epitaxy.