# US 10,312,158 B2 · Method for forming semiconductor device structure with gate structure

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- Number: US 10,312,158 B2
- Document ID: US10312158B2
- Status: Granted
- Kind: B2
- Application number: 15/670,401
- Filed: 2017-08-07
- Published: 2019-02-07
- Granted: 2019-06-04
- Earliest claimed: 2017-08-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yi-Cheng Li; Chien-Hao Chen; Yung-Cheng Lu; Jr-Jung Lin; Chun-Hung Lee; Chao-Cheng Chen
- Web page: https://patentgrep.com/patent/US10312158B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 64/0133: {at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/662: {the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion. The method includes annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer. The method includes forming a second amorphous layer over the first polycrystalline layer. The method includes removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion. The remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.

## Claims

### Claim 1

A method for forming a semiconductor device structure, comprising:
forming a first amorphous layer over a substrate, wherein the substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion;
annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer;
forming a second amorphous layer over the first polycrystalline layer; and
removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion, wherein the remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.

### Claim 2 (depends on 1)

The method for forming a semiconductor device structure as claimed in claim 1, further comprising:
before the annealing of the first amorphous layer, forming a second polycrystalline layer over the first amorphous layer; and
after the annealing of the first amorphous layer, removing the second polycrystalline layer and an upper portion of the first polycrystalline layer.

### Claim 3 (depends on 1)

The method for forming a semiconductor device structure as claimed in claim 1, wherein the first fin portion has a top surface, and a first thickness of the first polycrystalline layer over the top surface is less than a second thickness of the second amorphous layer.

### Claim 4 (depends on 1)

The method for forming a semiconductor device structure as claimed in claim 1, further comprising:
after the annealing of the first amorphous layer, thinning the first polycrystalline layer from a top surface of the first polycrystalline layer.

### Claim 5 (depends on 1)

The method for forming a semiconductor device structure as claimed in claim 1, wherein the first fin portion has a first sidewall, and the first sidewall has a first recess.

### Claim 6 (depends on 5)

The method for forming a semiconductor device structure as claimed in claim 5, wherein the substrate further has a second fin portion, the second fin portion has a second sidewall facing the first sidewall, the second sidewall has a second recess, and the first amorphous layer further covers the second fin portion and has a void between the first recess and the second recess.

### Claim 7 (depends on 6)

The method for forming a semiconductor device structure as claimed in claim 6, wherein the forming of the first amorphous layer comprises:
depositing a first amorphous material layer over the substrate to cover the first fin portion and the second fin portion;
removing a portion of the first amorphous material layer between the first fin portion and the second fin portion; and
depositing a second amorphous material layer over the first amorphous material layer.

### Claim 8 (depends on 1)

The method for forming a semiconductor device structure as claimed in claim 1, further comprising:
after the formation of the first gate structure, forming a spacer layer over sidewalls of the first gate structure;
forming a dielectric layer over the substrate and surrounding the first gate structure and the spacer layer;
removing the first gate structure, wherein an opening is formed in the spacer layer after the removing of the first gate structure; and
forming a second gate structure in the opening.

### Claim 9 (depends on 1)

The method for forming a semiconductor device structure as claimed in claim 1, further comprising:
before the forming of the second amorphous layer, forming a semiconductor oxide layer over the first polycrystalline layer, wherein the second amorphous layer is formed over the semiconductor oxide layer, and the removing of the first portion and the second portion further comprises removing the semiconductor oxide layer between the first portion and the second portion.

### Claim 10 (depends on 1)

The method for forming a semiconductor device structure as claimed in claim 1, further comprising:
before the forming of the second amorphous layer, forming a semiconductor oxide layer over the first polycrystalline layer; and
removing the semiconductor oxide layer, wherein the second amorphous layer is in direct contact with the first polycrystalline layer.

### Claim 11

A method for forming a semiconductor device structure, comprising:
forming an amorphous layer over a substrate, wherein the substrate has a base portion and a fin portion over the base portion, and the amorphous layer covers the fin portion;
annealing the amorphous layer to crystallize the amorphous layer into a first polycrystalline layer;
before the annealing of the amorphous layer, forming a second polycrystalline layer over the amorphous layer;
forming a semiconductor layer over the first polycrystalline layer, wherein a first average grain diameter of the semiconductor layer is less than a second average grain diameter of the first polycrystalline layer; and
removing a first portion of the semiconductor layer and a second portion of the first polycrystalline layer under the first portion, wherein the remaining semiconductor layer and the remaining first polycrystalline layer under the remaining semiconductor layer together form a first gate structure over and across the fin portion.

### Claim 12 (depends on 11)

The method for forming a semiconductor device structure as claimed in claim 11, further comprising:
after the annealing of the amorphous layer, removing the second polycrystalline layer and an upper portion of the first polycrystalline layer.

### Claim 13 (depends on 11)

The method for forming a semiconductor device structure as claimed in claim 11, wherein the fin portion has a top surface, and a first thickness of the first polycrystalline layer over the top surface is less than a second thickness of the semiconductor layer.

### Claim 14 (depends on 11)

The method for forming a semiconductor device structure as claimed in claim 11, further comprising:
after the formation of the first gate structure, forming a spacer layer over sidewalls of the first gate structure;
forming a dielectric layer over the substrate and surrounding the first gate structure and the spacer layer;
removing the first gate structure, wherein an opening is formed in the spacer layer after the removing of the first gate structure; and
forming a second gate structure in the opening.

### Claim 15

A method for forming a semiconductor device structure, comprising:
forming a first semiconductor layer over a substrate, wherein the substrate has a base portion and a fin portion over the base portion, the first semiconductor layer covers the fin portion, and the first semiconductor layer has a first average grain diameter;
performing an annealing process on the first semiconductor layer, wherein the first average grain diameter is enlarged by the annealing process;
after the annealing process, forming a second semiconductor layer over the first semiconductor layer, wherein a second average grain diameter of the second semiconductor layer is less than the enlarged first average grain diameter of the first semiconductor layer; and
removing a first portion of the second semiconductor layer and a second portion of the first semiconductor layer under the first portion, wherein the remaining second semiconductor layer and the remaining first semiconductor layer under the remaining second semiconductor layer together form a gate structure over and across the fin portion, wherein the removing of the first portion and the second portion comprises:
performing a first etching process on the second semiconductor layer to remove the first portion, wherein the second portion of the first semiconductor layer under the first portion is exposed after the first etching process; and
after the first etching process, performing a second etching process on the first semiconductor layer using the second semiconductor layer as an etching mask to remove the second portion.

### Claim 16 (depends on 15)

The method for forming a semiconductor device structure as claimed in claim 15, further comprising:
before the forming of the second semiconductor layer, forming a semiconductor oxide layer over the first semiconductor layer, wherein the second semiconductor layer is formed over the semiconductor oxide layer, and the removing of the first portion and the second portion further comprises removing the semiconductor oxide layer between the first portion and the second portion.

### Claim 17 (depends on 15)

The method for forming a semiconductor device structure as claimed in claim 15, further comprising:
before the forming of the second semiconductor layer, forming a semiconductor oxide layer over the first semiconductor layer; and
removing the semiconductor oxide layer, wherein the second semiconductor layer is in direct contact with the first semiconductor layer.

### Claim 18 (depends on 15)

The method for forming a semiconductor device structure as claimed in claim 15, further comprising:
after the annealing of the first semiconductor layer, thinning the first semiconductor layer from a top surface of the first semiconductor layer.

### Claim 19 (depends on 1)

The method for forming a semiconductor device structure as claimed in claim 1, wherein the substrate further has a second fin portion, and the first amorphous layer further covers the second fin portion and has a void between the first fin portion and the second fin portion.

### Claim 20 (depends on 1)

The method for forming a semiconductor device structure as claimed in claim 1, wherein the removing of the first portion and the second portion comprises:
performing a first etching process on the second amorphous layer to remove the first portion, wherein the second portion of the first polycrystalline layer under the first portion is exposed after the first etching process; and
after the first etching process, performing a second etching process on the first polycrystalline layer using the second amorphous layer as an etching mask to remove the second portion.