# US 10,312,157 B2 · Field effect transistor stack with tunable work function

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- Number: US 10,312,157 B2
- Document ID: US10312157B2
- Status: Granted
- Kind: B2
- Application number: 15/795,414
- Filed: 2017-10-27
- Published: 2018-02-15
- Granted: 2019-06-04
- Earliest claimed: 2016-01-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ruqiang Bao; Siddarth A. Krishnan; Unoh Kwon; Vijay Narayanan
- Web page: https://patentgrep.com/patent/US10312157B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/853: {comprising FinFETs}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

## Claims

### Claim 1

A method for fabricating a gate stack of a semiconductor device, the method comprising:
forming a first dielectric layer over a channel region of the device;
forming a first nitride layer comprising TaN over the first dielectric layer;
forming a first gate metal layer comprising NbAlC over the first nitride layer;
forming a capping layer comprising a nitride over the first gate metal layer;
removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, the remaining portions of the capping layer and the first gate metal layer and the first nitride layer defining a strong oxygen scavenging niobium aluminum carbonitride stack comprising a first thickness in a n-type field effect transistor (nFET) region of the gate stack;
depositing a scavenging layer comprising TiAlC or NbAlC on the first nitride layer in the pFET region and on the capping layer in the nFET region such that the scavenging layer and the first nitride layer in the nFET region are formed on opposite ends of the strong oxygen scavenging niobium aluminum carbonitride stack; and
depositing a second nitride layer comprising TiN or TaN on the scavenging layer in both the pFET region and the nFET region such that the second nitride layer, the scavenging layer, and the first nitride layer in the pFET region define a weak oxygen scavenging stack comprising a second thickness and wherein the second nitride layer and the capping layer are of the same composition;
wherein the first thickness is greater than the second thickness and the second thickness is selected to adjust a threshold voltage in the pFET region and to ensure that the weak oxygen scavenging stack is relatively weaker than the strong oxygen scavenging stack.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first dielectric layer includes an oxide material.

### Claim 3 (depends on 1)

The method of claim 1, wherein the capping layer comprises TiN.

### Claim 4 (depends on 1)

The method of claim 1, further comprising depositing a gate electrode material on the second nitride layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the gate electrode material comprises W.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming a source/drain region adjacent to the gate stack prior to forming the gate stack.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming a sacrificial gate stack over the channel region of the device prior to forming the gate stack.

### Claim 8 (depends on 7)

The method of claim 7, further comprising forming a spacer along sidewalls of the sacrificial gate stack.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming a layer of insulator material around the spacer.

### Claim 10 (depends on 9)

The method of claim 9, further comprising removing the sacrificial gate stack to expose the channel region of the device.