# US 10,312,156 B2 · Vertical fin field effect transistor (V-FinFET), semiconductor device having V-FinFET and method of fabricating V-FinFET

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- Number: US 10,312,156 B2
- Document ID: US10312156B2
- Status: Granted
- Kind: B2
- Application number: 15/838,665
- Filed: 2017-12-12
- Published: 2018-04-26
- Granted: 2019-06-04
- Earliest claimed: 2016-06-16
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Soo Yeon Jeong; Myung Gil Kang
- Web page: https://patentgrep.com/patent/US10312156B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/837: {comprising vertical IGFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/853: {comprising FinFETs}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an upper surface of the lower S/D. The fin structure includes a sidewall having an upper sidewall portion, a lower sidewall portion and a center sidewall portion positioned therebetween. An upper S/D is disposed on an upper surface of the fin structure. An upper spacer is disposed on the upper sidewall portion. A lower spacer is disposed on the lower sidewall portion. A stacked structure including a gate oxide layer and a first gate electrode is disposed on an upper surface of the lower spacer, the center sidewall portion and a lower surface of the upper spacer. A second gate electrode is disposed on the first gate electrode.

## Claims

### Claim 1

A method of fabricating a vertical fin field effect transistor (V-FinFET), comprising:
forming a lower source/drain (S/D) in a substrate;
forming a preliminary stacked structure on the substrate, the preliminary stacked structure including a preliminary lower spacer layer, a sacrificial layer and a preliminary upper spacer layer stacked on each other;
forming a first trench penetrating the preliminary stacked structure to expose the lower S/D;
forming a fin structure in the first trench and on the lower S/D;
forming an upper S/D on the fin structure and the preliminary stacked structure;
forming a capping layer on the fin structure covering the upper S/D;
forming a second trench penetrating the preliminary upper spacer layer and the sacrificial layer;
removing the sacrificial layer exposed through the second trench so that a sidewall of the fin structure is exposed;
forming a preliminary gate oxide layer within the second trench;
forming a preliminary gate electrode on the preliminary gate oxide layer within the second trench; and
patterning the preliminary gate oxide layer and the preliminary gate electrode using the capping layer as a mask so that a gate oxide layer and a first gate electrode are formed, respectively, and
wherein the fin structure is epitaxially grown from the lower S/D.

### Claim 2 (depends on 1)

The method of claim 1,
wherein the forming of the preliminary stacked structure includes:
forming a preliminary lower spacer layer on the substrate;
forming a sacrificial layer on the preliminary lower spacer layer; and
forming a preliminary upper spacer layer on the sacrificial layer,
wherein the sacrificial layer is interposed between the preliminary lower spacer layer and the preliminary upper spacer layer.

### Claim 3 (depends on 2)

The method of claim 2,
wherein the sacrificial layer is formed of a different material from materials of the preliminary lower spacer layer and the preliminary upper spacer layer.

### Claim 4 (depends on 3)

The method of claim 3,
wherein the sacrificial layer is formed of silicon or silicon oxide, and
wherein the preliminary lower spacer layer and the preliminary upper spacer layer are formed of silicon nitride.

### Claim 5 (depends on 1)

The method of claim 1,
wherein the first gate electrode includes TiN, TaN or TiAlC.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming a second gate electrode on the first gate electrode; and
forming a gate contact electrode on the second gate electrode,
wherein the capping layer aligns the second gate electrode and the gate contact electrode.

### Claim 7 (depends on 1)

The method of claim 1, wherein the gate oxide layer includes a C-shaped portion.