# US 10,312,155 B2 · FinFET device and fabrication method thereof

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- Number: US 10,312,155 B2
- Document ID: US10312155B2
- Status: Granted
- Kind: B2
- Application number: 15/784,357
- Filed: 2017-10-16
- Published: 2018-04-19
- Granted: 2019-06-04
- Earliest claimed: 2016-10-18
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Yong Li
- Web page: https://patentgrep.com/patent/US10312155B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10P 32/1408: {from or through or into an external applied layer, e.g. photoresist or nitride layers}
- H10P 32/171: {being group IV material}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 84/853: {comprising FinFETs}
- H10P 32/141: {the applied layer comprising oxides only}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A FinFET device and fabrication method thereof is provided. The fabrication method include: providing a semiconductor substrate with a fin protruding from the semiconductor substrate, and a gate structure across a length portion of the fin and covering a portion of the fin; etching a partial thickness of the fin on both sides of the gate structure to form grooves; forming a doped layer in a bottom and sidewalls of the grooves; annealing the doped layer to allow the doping ions to diffuse into the fin and to form a lightly doped source/drain region; removing the doped layer after the annealing; and forming epitaxial layers to fill up the grooves.

## Claims

### Claim 1

A method for fabricating FinFET, comprising:
providing a semiconductor substrate with a fin protruding from the semiconductor substrate, and a gate structure on the semiconductor substrate across a length portion of the fin and covering a portion of a top and sidewalls of the fin;
forming a mask layer on the semiconductor substrate, the top and sidewalls of the fin on both sides of the gate structure;
etching a partial thickness of the fin on both sides of the gate structure to form grooves;
forming a doped layer with doping ions in a bottom and sidewalls of the grooves;
annealing the doped layer to allow the doping ions to diffuse into the fin and to form lightly doped source/drain regions;
removing the doped layer after the annealing; and
forming epitaxial layers to fill up the grooves.

### Claim 2 (depends on 1)

The method for fabricating the FinFET according to claim 1,
wherein forming the mask layer on the semiconductor substrate, the top and sidewalls of the fin on both sides of the gate structure includes:
forming an initial mask layer on the semiconductor substrate, the top and sidewalls of the fin before forming the grooves;
removing a first portion of the initial mask layer on the top and sidewalls of the part of the fin on both sides of the gate structure to be etched in the etching process of forming the grooves; and
retaining a second portion of the initial mask layer on the sidewalls of the remaining fin on both sides of the gate structure to form the mask layer.

### Claim 3 (depends on 2)

The method for fabricating the FinFET according to claim 2, wherein the doped layer is formed on the mask layer on the sidewalls of the remaining fin.

### Claim 4 (depends on 2)

The method for fabricating the FinFET according to claim 2, wherein a top of the mask layer and a top of the remaining fin are coplanar with each other.

### Claim 5 (depends on 1)

The method for fabricating the FinFET according to claim 1, wherein the doped layer is made of a material including SiO2, SiN, SiOxNy, SiC, SiOxCy or SiNCO.

### Claim 6 (depends on 1)

The method for fabricating the FinFET according to claim 1, wherein a thickness of the doped layer is about 2 nm to about 10 nm.

### Claim 7 (depends on 1)

The method for fabricating the FinFET according to claim 1, wherein annealing the doped layer includes a spike annealing or a laser annealing.

### Claim 8 (depends on 1)

The method for fabricating the FinFET according to claim 1, wherein a temperature for annealing the doped layer is about 900° C. to about 1100° C.

### Claim 9 (depends on 1)

The method for fabricating the FinFET according to claim 1, wherein removing the doped layer includes a wet etching method.

### Claim 10 (depends on 1)

The method for fabricating the FinFET according to claim 1, wherein the epitaxial layers are formed by a selective epitaxial growth process.

### Claim 11 (depends on 10)

The method for fabricating the FinFET according to claim 10, wherein the epitaxial layers are in-situ doped with doping ions same type as in the doping ions in the doped layer.

### Claim 12 (depends on 10)

The method for fabricating the FinFET according to claim 10, wherein the epitaxial layers are doped after forming the epitaxial layers and have doping ions same type as the doping ions in the doped layer.

### Claim 13 (depends on 10)

The method for fabricating the FinFET according to claim 10, wherein:
the semiconductor substrate includes a PMOS and an NMOS region,
fins are located on both the PMOS and the NMOS region; and
gate structures includes a first gate structure in the PMOS region and a second gate structure in the NMOS region, and
the method further includes:
etching a partial thickness of the fin to form first grooves on both sides of the first gate structure;
forming a first doped layer on a bottom and sidewalls of the first grooves with P-type ions;
annealing the first doped layer to allow the P-type ions to diffuse into the fin on the PMOS region to form a first lightly doped source/drain region;
removing the first doped layer;
forming first epitaxial layers to fill up the first grooves;
etching a partial thickness of the fin on both sides of the second gate structure to form second grooves;
forming a second doped layer on a bottom and sidewalls of the second grooves with N-type ions;
annealing the second doped layer to allow the N-type ions to diffuse to the fin on the NMOS region to form a second lightly doped source/drain region;
removing the second doped layer; and
forming second epitaxial layers to fill up the second grooves.

### Claim 14 (depends on 13)

The method for fabricating the FinFET according to claim 13, further including:
forming a first mask layer on the semiconductor substrate, on top and sidewalls of the fins in the PMOS region and the NMOS region; and
when forming the first grooves, removing a portion of the first mask layer on the top and sidewalls of the fin in the PMOS region.

### Claim 15 (depends on 14)

The method for fabricating the FinFET according to claim 14, further including:
forming a first patterned layer on the first mask layer in the NMOS region and on a portion of the first mask layer of the PMOS region, and
before forming the first grooves, etching the exposed portion of the first mask layer in the PMOS region and a partial thickness of the fin by using the first patterned layer as an etch mask.

### Claim 16 (depends on 14)

The method for fabricating the FinFET according to claim 14, wherein the first doped layer is further located on the first mask layer in the NMOS region and on the first mask layer on sidewalls of the remaining fin in the PMOS region.

### Claim 17 (depends on 13)

The method for fabricating the FinFET according to claim 13, wherein:
the second grooves are formed after forming the first grooves;
a second mask layer is formed on the first epitaxial layers, on the first mask layer in the PMOS region and the NMOS region; and
the second grooves are formed by:
forming a second patterned layer on the second mask layer in the PMOS region and on a portion of the second mask layer in the NMOS region, and
etching the second mask layer, the first mask layer and a partial thickness of the fin in the NMOS region by using the second patterned layer as an etch mask.

### Claim 18 (depends on 10)

The method for fabricating the FinFET according to claim 10, further including:
forming an isolation layer on the semiconductor substrate and covering a portion of the sidewalls of the fins, wherein the isolation layer has a top lower than a top of the fins.

### Claim 19 (depends on 1)

The method for fabricating the FinFET according to claim 1, wherein the sidewalls of the grooves have a surface coinciding with a surface of the mask layer on a side surface of the gate structure.