# US 10,312,154 B2 · Method of forming vertical FinFET device having self-aligned contacts

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- Number: US 10,312,154 B2
- Document ID: US10312154B2
- Status: Granted
- Kind: B2
- Application number: 15/705,888
- Filed: 2017-09-15
- Published: 2019-03-21
- Granted: 2019-06-04
- Earliest claimed: 2017-09-15
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Ruilong Xie; Steven Bentley; Puneet Harischandra Suvarna; Chanro Park; Min Gyu Sung; Lars Liebmann; Su Chen Fan; Brent Anderson
- Web page: https://patentgrep.com/patent/US10312154B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0225: {using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/011: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

## Claims

### Claim 1

A method of forming a vertical FinFET device, comprising:
etching an opening in a hard mask disposed over a semiconductor fin, the opening extending through a portion of the semiconductor fin to expose an endwall of the semiconductor fin and a top surface of a bottom source/drain region disposed laterally adjacent to the endwall;
forming a sidewall spacer within the opening, wherein the sidewall spacer is formed over the exposed endwall of the semiconductor fin;
forming a top source/drain region over an upper portion of the semiconductor fin and a top source/drain metallization layer over the top source/drain region; and
forming a bottom source/drain metallization layer over the bottom source drain region within the opening, wherein the sidewall spacer is disposed between the top source/drain metallization layer and the bottom source/drain metallization layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the sidewall spacer thickness ranges from 4 to 20 nm.

### Claim 3 (depends on 1)

The method of claim 1, wherein the sidewall spacer is formed over the entire exposed endwall surface of the fin.

### Claim 4 (depends on 1)

The method of claim 1, wherein the sidewall spacer is formed within the opening over a sidewall surface of the hard mask.

### Claim 5 (depends on 1)

The method of claim 1, wherein the sidewall spacer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, SiOC, SiOCN and SiBCN.

### Claim 6

A method of forming a vertical FinFET device, comprising:
forming a hard mask over a semiconductor substrate;
forming a fin over the semiconductor substrate using the hard mask as an etch mask;
forming a bottom source/drain region over the semiconductor substrate, where a lower portion of the fin is in contact with the bottom source/drain region;
forming a gate stack over sidewalls of the fin, the gate stack extending laterally over the bottom source/drain region on at least one side of the fin, wherein the gate stack comprises a gate dielectric and a gate conductor formed over the gate dielectric;
etching an opening in the hard mask and through a portion of the fin to expose an endwall of the fin and a top surface of the bottom source/drain region laterally adjacent to the endwall;
forming a sidewall spacer within the opening, wherein the sidewall spacer is formed over the exposed endwall of the fin;
forming a top source/drain region over an upper portion of the fin and a top source/drain metallization layer over the top source/drain region; and
forming a bottom source/drain metallization layer over the bottom source drain region, wherein the top source/drain metallization layer is formed over a first side of the sidewall spacer and the bottom source/drain metallization layer is formed over a second side of the sidewall spacer opposite to the first side.

### Claim 7 (depends on 6)

The method of claim 6, further comprising forming a bottom spacer over the bottom source/drain region laterally adjacent to the fin prior to forming the gate stack.

### Claim 8 (depends on 6)

The method of claim 6, further comprising etching the gate stack to recess the gate stack to a height below a top surface of the fin.

### Claim 9 (depends on 6)

The method of claim 6, wherein the sidewall spacer is formed directly over the exposed endwall of the fin.

### Claim 10 (depends on 6)

The method of claim 6, wherein the sidewall spacer thickness is 4 to 20 nm.

### Claim 11 (depends on 6)

The method of claim 6, wherein the sidewall spacer is formed over the entire exposed endwall surface of the fin.

### Claim 12 (depends on 6)

The method of claim 6, wherein the sidewall spacer is formed within the opening over a sidewall surface of the hard mask.

### Claim 13 (depends on 6)

The method of claim 6, wherein the sidewall spacer is formed over exposed surfaces of the gate stack within the opening.

### Claim 14 (depends on 6)

The method of claim 6, wherein forming the top source/drain region comprises removing the hard mask to expose a top surface of the fin.

### Claim 15 (depends on 6)

The method of claim 6, wherein a distance between a sidewall of the bottom source/drain metallization layer and the endwall of the fin is 4 to 20 nm.

### Claim 16 (depends on 6)

The method of claim 6, further comprising forming a gate metallization layer in electrical contact with the gate conductor.