# US 10,312,153 B2 · Semiconductor devices having FIN active regions

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- Number: US 10,312,153 B2
- Document ID: US10312153B2
- Status: Granted
- Kind: B2
- Application number: 15/914,125
- Filed: 2018-03-07
- Published: 2018-07-12
- Granted: 2019-06-04
- Earliest claimed: 2015-03-20
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kyungin Choi; Ah-Young Cheon; Kwang-Yong Yang; Myungil Kang; Dohyoung Kim; YoonHae Kim
- Web page: https://patentgrep.com/patent/US10312153B2

## CPC

- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising:
forming sacrificial patterns on a substrate;
forming an ion implanted region in the substrate between the sacrificial patterns;
etching a portion of the substrate and the ion implanted region to form a recess region between the sacrificial patterns;
forming a source/drain epitaxial layer in the recess region;
forming active fins by etching the substrate before forming the sacrificial patterns, and
replacing the sacrificial patterns by gate patterns after forming the source/drain epitaxial layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the etching of the portion of the substrate and the ion implanted region comprises:
performing an isotropic etching process; and
performing an anisotropic etching process,
wherein the recess region is formed to have an inflection point such that an upper width of the recess region is greater than a lower width of the recess region.

### Claim 3 (depends on 1)

The method of claim 1, wherein:
the forming of the ion implanted region is performed by diagonal ion implantation process; and
the forming of the ion implanted region comprises ion implanted regions that are separated from each other between the sacrificial patterns.

### Claim 4 (depends on 3)

The method of claim 3, wherein the etching of the portion of the substrate and the ion implanted region comprises performing an isotropic etching process and performing an anisotropic etching process to remove the portion of the substrate and the ion implanted regions between the sacrificial patterns,
wherein the recess region is formed to have an inflection point such that an upper width of the recess region is greater than a lower width of the recess region.

### Claim 5 (depends on 1)

The method of claim 1, wherein the etching of the portion of the substrate and the ion implanted region comprises:
performing an anisotropic-etching process; and
performing an isotropic etching process,
wherein the recess region is formed to have vertically flat sidewalls.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming spacers to be in contact with sidewalls of each of the sacrificial patterns,
wherein the recess region exposes lower surfaces of the spacers.

### Claim 7 (depends on 1)

The method of claim 1, wherein the forming of the ion implanted region comprises:
forming an ion implantation buffer layer on the substrate; and
performing ion-implantation process to implant ions into the substrate; and
removing the ion implantation buffer layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein each of the sacrificial patterns comprises an insulation pattern, a polysilicon pattern and a hard mask that is sequentially stacked.

### Claim 9

A method of forming a semiconductor device, comprising:
providing a substrate having a first region and a second region;
forming sacrificial patterns on the substrate of the first region and the second region;
forming an ion implanted region in the substrate between the sacrificial patterns at the second region;
forming a first recess region by etching a portion of the substrate between the sacrificial patterns at the first region;
forming a second recess region by etching another portion of the substrate and the ion implanted region at the second region;
forming a first source/drain epitaxial layer in the first recess region; and
forming a second source/drain epitaxial layer in the second recess region.

### Claim 10 (depends on 9)

The method of claim 9, wherein the forming of the ion implanted region in the substrate between the sacrificial patterns at the second region is performed by masking the substrate of the first region.

### Claim 11 (depends on 10)

The method of claim 10, further comprising: forming another ion implanted region in the substrate between the sacrificial patterns at the first region,
wherein the ion implanted region of the second region and another ion implanted region of the first region are simultaneously formed.

### Claim 12 (depends on 11)

The method of claim 11, wherein the etching of the portion of the substrate at the first region comprises etching another ion implanted region to form the first recess region.

### Claim 13 (depends on 11)

The method of claim 11, wherein at least one of the forming of the first recess region and the forming of the second recess region is performed by:
performing an isotropic etching process; and
performing an anisotropic etching process,
wherein a sidewall profile of at least one of the first recess region and the second recess region has an inflection point.

### Claim 14 (depends on 11)

The method of claim 11, wherein the forming of the another ion implanted region at the first region and the forming of the ion implanted region at the second region are performed by diagonal ion implantation process to form first ion implanted regions that are separated from each other between the sacrificial patterns at the first region and to form second ion implanted regions that are separated from each other between the sacrificial patterns at the second region.

### Claim 15 (depends on 14)

The method of claim 14, wherein each of the forming of the first recess region and the forming of the second recess region is performed by:
performing an isotropic etching process; and
performing an anisotropic etching process,
wherein a sidewall profile of each of the first recess region and the second recess region has an inflection point.

### Claim 16 (depends on 9)

The method of claim 9, wherein at least one of the forming of the first recess region and the forming of the second recess region is performed by:
performing an anisotropic etching process; and
performing an isotropic etching process,
wherein a sidewall profile of at least one of the first recess region and the second recess region is vertically flat.

### Claim 17 (depends on 9)

The method of claim 9, further comprising:
forming spacers to be in contact with sidewalls of each of the sacrificial patterns,
wherein each of the first recess region and the second recess region exposes lower surfaces of the spacers.

### Claim 18 (depends on 9)

The method of claim 9, further comprising:
forming a protection layer to cover the first source/drain epitaxial layer in the first recess region before forming the second source/drain epitaxial layer; and
removing the protection layer after forming the second source/drain epitaxial layer.

### Claim 19 (depends on 9)

The method of claim 9, wherein the forming of the ion implanted region comprises:
forming an ion implantation buffer layer on the substrate;
performing ion-implantation process to implant ions into the substrate; and
removing the ion implantation buffer layer.