# US 10,312,152 B2 · Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,312,152 B2
- Document ID: US10312152B2
- Status: Granted
- Kind: B2
- Application number: 15/818,657
- Filed: 2017-11-20
- Published: 2018-04-26
- Granted: 2019-06-04
- Earliest claimed: 2016-10-24
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Mark S. Rodder; Borna J. Obradovic; Joon Goo Hong; Seung Hun Lee; Pan Kwi Park; Seung Ryul Lee
- Web page: https://patentgrep.com/patent/US10312152B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/514: {characterised by the insulating layers}
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions and a dielectric separation region extending completely between first and second nanowire-like channel regions of the stack. The nFET and the pFET each also include a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions. The channel heights of the nanowire-like channel regions of the partial GAA nFET and the partial GAA pFET are different.

## Claims

### Claim 1

A CMOS circuit, comprising:
a partial gate-all-around (GAA) nFET; and
a partial GAA pFET, wherein the partial GAA nFET and the partial GAA pFET each comprise:
a fin comprising a stack of nanowire-like channel regions, the stack comprising at least a first nanowire-like channel region and a second nanowire-like channel region stacked on the first nanowire-like channel region;
a dielectric separation region between the first and second nanowire-like channel regions, the dielectric separation region extending completely from a surface of the second nanowire-like channel region facing the first nanowire-like channel region to a surface of the first nanowire-like channel region facing the second nanowire-like channel region;
a source electrode and a drain electrode on opposite sides of the fin; and
a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions, the gate stack comprising a gate dielectric layer and a metal layer on the gate dielectric layer,
wherein the metal layer of the gate stack does not extend between the first and second nanowire-like channel regions, and
wherein an nFET channel height of each of the first and second nanowire-like channel regions of the partial GAA nFET is different than a pFET channel height of each of the first and second nanowire-like channel regions of the partial GAA pFET.

### Claim 2 (depends on 1)

The CMOS circuit of claim 1, wherein the nFET channel height is less than the pFET channel height.

### Claim 3 (depends on 2)

The CMOS circuit of claim 2, wherein the nFET channel height is from approximately 2 nm to approximately 6 nm, and wherein the pFET channel height is from approximately 4 nm to approximately 6 nm.

### Claim 4 (depends on 2)

The CMOS circuit of claim 2, wherein the nFET channel height is from approximately 3 nm to approximately 4 nm, and wherein the pFET channel height is from approximately 4 nm to approximately 5 nm.

### Claim 5 (depends on 1)

The CMOS circuit of claim 1, wherein a height of the dielectric separation region of the partial GAA nFET is different than a height of the dielectric separation region of the partial GAA pFET.

### Claim 6 (depends on 5)

The CMOS circuit of claim 5, wherein the height of the dielectric separation region of the partial GAA nFET is greater than the height of the dielectric separation region of the pFET.

### Claim 7 (depends on 1)

The CMOS circuit of claim 1, wherein a first sum of the nFET channel height and a height of the dielectric separation region of the partial GAA nFET is substantially equal to a second sum of the pFET channel height and a height of the dielectric separation region of the partial GAA pFET.

### Claim 8 (depends on 7)

The CMOS circuit of claim 7, wherein the first and second sums are each from approximately 5 nm to approximately 12 nm.

### Claim 9 (depends on 1)

The CMOS circuit of claim 1, wherein the dielectric separation regions of the partial GAA nFET and the partial GAA pFET each comprise a portion of the gate dielectric layer of the gate stack.

### Claim 10 (depends on 1)

The CMOS circuit of claim 1, wherein a dielectric material of the dielectric separation region of the partial GAA nFET and the partial GAA pFET is different than a dielectric material of the gate dielectric layer of the partial GAA nFET and the partial GAA pFET.

### Claim 11 (depends on 1)

The CMOS circuit of claim 1, wherein the gate dielectric layer has a thickness from approximately 1 nm to approximately 3 nm.

### Claim 12 (depends on 1)

The CMOS circuit of claim 1, wherein the first and second nanowire-like channel regions of the partial GAA nFET or the partial GAA pFET each have a width from approximately 3 nm to approximately 8 nm.

### Claim 13

A method of forming a CMOS circuit comprising a partial gate-all-around (GAA) nFET and a partial GAA pFET, the method comprising:
forming a stack of alternating sacrificial layers and conducting channel layers on a substrate;
etching the stack to form a first fin of the partial GAA nFET and a second fin of the partial GAA pFET, each of the first and second fins comprising a stack of nanowire-like channel regions, the stack comprising at least a first nanowire-like channel region and a second nanowire-like channel region stacked on the first nanowire-like channel region;
forming source and drain electrodes for the partial GAA nFET;
forming source and drain electrodes for the partial GAA pFET;
masking the second fin of the partial GAA pFET;
removing a portion of the stack of nanowire-like channel regions of the first fin such that a height of each of the first and second nanowire-like channel regions of the first fin is less than a height of each of the first and second nanowire-like channel regions of the second fin;
forming, for each of the first and second fins, a dielectric separation region between the first and second nanowire-like channel regions of the stack of nanowire-like channel regions, the dielectric separation region extending completely from a surface of the second nanowire-like channel region facing the first nanowire-like channel region to a surface of the first nanowire-like channel region facing the second nanowire-like channel region; and
forming a gate stack comprising a gate dielectric layer and a metal layer on the gate dielectric layer,
wherein the gate stack extends along a pair of sidewalls of the stack of nanowire-like channel regions for each of the first and second fins, and
wherein, for each of the first and second fins, the metal layer of the gate stack does not extend between the first and second nanowire-like channel regions of the stack of nanowire-like channel regions.

### Claim 14 (depends on 13)

The method of claim 13, wherein the removing the portion of the stack of nanowire-like channel regions of the first fin comprises a process or processes selected from the group consisting of a strip process, a cleaning process, an ashing process, an etching process, an oxidation process, and combinations thereof.

### Claim 15 (depends on 13)

The method of claim 13, wherein the dielectric separation region of the first fin or the second fin is formed during the forming of the gate stack, and wherein the dielectric separation region of the first fin or the second fin comprises a portion of the gate dielectric layer of the gate stack.

### Claim 16 (depends on 13)

The method of claim 13, wherein the dielectric separation region of each of the first and second fins is formed before the forming of the gate stack, and wherein a material of the dielectric separation region of each of the first and second fins is different than a material of the gate dielectric layer.

### Claim 17 (depends on 13)

The method of claim 13, wherein the forming the source and drain electrodes of the partial GAA pFET comprises depositing an Si buffer layer followed by depositing a layer of SiGe or SiGeB.

### Claim 18 (depends on 13)

The method of claim 13, wherein the forming the source and drain electrodes of the partial GAA nFET comprises depositing an Si layer.

### Claim 19 (depends on 13)

The method of claim 13, wherein the conducting channel layers comprise Si, the sacrificial layers comprise SiGe, and wherein Ge content of the SiGe is from approximately 10% to approximately 50%.

### Claim 20 (depends on 13)

The method of claim 13, further comprising removing a portion of the stack of nanowire-like channel regions of the second fin, wherein the removing of the portion of the stack of nanowire-like channel regions of the first fin is greater than the removing of the portion of the stack of nanowire-like channel regions of the second fin.