# US 10,312,150 B1 · Protected trench isolation for fin-type field-effect transistors

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- Number: US 10,312,150 B1
- Document ID: US10312150B1
- Status: Granted
- Kind: B1
- Application number: 15/919,594
- Filed: 2018-03-13
- Granted: 2019-06-04
- Earliest claimed: 2018-03-13
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Fuad Al-Amoody; Jinping Liu; Joseph Kassim; Bharat Krishnan
- Web page: https://patentgrep.com/patent/US10312150B1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10P 14/61: using masks
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 14/69394: {the material containing titanium, e.g. TiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 70/23: {during, before or after processing of insulating materials}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of forming a fin-type field-effect transistor. A gate structure is formed that extends across a plurality of semiconductor fins. A spacer layer composed of a dielectric material is conformally deposited over the gate structure, the semiconductor fins, and a dielectric layer in gaps between the semiconductor fins. A protective layer is conformally deposited over the spacer layer. The protective layer over the dielectric layer in the gaps between the semiconductor fins is masked, and the protective layer is then removed from the gate structure and the semiconductor fins selective to the dielectric material of the spacer layer.

## Claims

### Claim 1

A method comprising:
forming a gate structure extending across a plurality of semiconductor fins;
depositing a spacer layer composed of a dielectric material conformally over the gate structure, the semiconductor fins, and a dielectric layer in gaps between the semiconductor fins;
depositing a protective layer conformally over the spacer layer;
masking the protective layer over the dielectric layer in the gaps between the semiconductor fins; and
after masking the protective layer over the dielectric layer in the gaps between the semiconductor fins, removing the protective layer from the gate structure and the semiconductor fins selective to the dielectric material of the spacer layer.

### Claim 2 (depends on 1)

The method of claim 1 wherein masking the protective layer over the dielectric layer in the gaps between the semiconductor fins comprises:
forming a hardmask layer over the protective layer on the gate structure, the semiconductor fins, and the dielectric layer in the gaps between the semiconductor fins.

### Claim 3 (depends on 2)

The method of claim 2 wherein the hardmask layer has a planar top surface when formed, and further comprising:
recessing the planar top surface of the hardmask layer relative to the gate structure and the semiconductor fins.

### Claim 4 (depends on 3)

The method of claim 3 wherein the planar top surface of the hardmask layer, after recessing, is arranged in a vertical direction between a top surface of the semiconductor fins and a top surface of the dielectric layer.

### Claim 5 (depends on 3)

The method of claim 3 wherein, after recessing, the hardmask layer has a thickness of less than or equal to 10 nanometers.

### Claim 6 (depends on 2)

The method of claim 2 wherein the hardmask layer is a spin-on hardmask.

### Claim 7 (depends on 2)

The method of claim 2 wherein the hardmask layer is a carbon-containing film.

### Claim 8 (depends on 2)

The method of claim 2 further comprising:
after removing the protective layer from the gate structure and the semiconductor fins, removing the hardmask layer from the protective layer over the dielectric layer arranged in the gaps between the semiconductor fins.

### Claim 9 (depends on 1)

The method of claim 1 wherein the protective layer is composed of aluminum dioxide.

### Claim 10 (depends on 1)

The method of claim 1 wherein the protective layer is composed of a nitride of silicon or titanium oxide.

### Claim 11 (depends on 1)

The method of claim 1 wherein the protective layer is selectively removed relative to the spacer layer by a wet clean or a wet chemical etch.

### Claim 12 (depends on 1)

The method of claim 1 wherein the protective layer over the dielectric layer in the gaps between the semiconductor fins is retained after removing the protective layer from the gate structure and the semiconductor fins.

### Claim 13 (depends on 1)

The method of claim 1 wherein the dielectric layer has a top surface that is planar, each of the semiconductor fins has a first section arranged above the top surface of the dielectric layer and a second section arranged below the top surface of the dielectric layer, and the spacer layer is arranged over the first section of each of the semiconductor fins.

### Claim 14 (depends on 1)

The method of claim 1 wherein the protective layer is composed of a material that is removable selective to silicon dioxide.

### Claim 15 (depends on 1)

The method of claim 1 wherein the protective layer is deposited after the gate structure is formed.

### Claim 16 (depends on 1)

The method of claim 1 further comprising:
after removing the protective layer from the gate structure and the semiconductor fins, performing a wet clean or a reactive ion etch with the protective layer over the dielectric layer in the gaps between the semiconductor fins.

### Claim 17 (depends on 1)

The method of claim 1 wherein the protective layer is deposited over the spacer layer by chemical vapor deposition or physical vapor deposition.

### Claim 18 (depends on 1)

The method of claim 1 wherein the spacer layer is arranged between the protective layer and a top surface of the dielectric layer in the gaps between the semiconductor fins.

### Claim 19 (depends on 18)

The method of claim 18 wherein the protective layer is in direct contact with the spacer layer.

### Claim 20 (depends on 1)

The method of claim 1 wherein the gate structure is cut before the protective layer is formed.