# US 10,312,148 B2 · Method and structure for forming MOSFET with reduced parasitic capacitance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,148 B2 - Document ID: US10312148B2 - Status: Granted - Kind: B2 - Application number: 15/856,309 - Filed: 2017-12-28 - Published: 2018-05-03 - Granted: 2019-06-04 - Earliest claimed: 2016-06-29 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Kangguo Cheng; Peng Xu; Chen Zhang - Web page: https://patentgrep.com/patent/US10312148B2 ## CPC - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/0285: {using formation of insulating sidewall spacers} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/6219: {characterised by the source or drain electrodes} - H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers} - H10D 64/671: {the conductor having lateral variation in doping or structure} - H10D 64/679: {comprising air gaps} - H10D 64/68: characterised by the insulator, e.g. by the gate insulator - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10D 84/0147: {Manufacturing their gate sidewall spacers} - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 20/48: Insulating materials thereof - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method (and structure) of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k sidewall spacer film, etching off the high-k sidewall spacer film from a top surface of the gate structure and from a portion of vertical walls of the gate structure. The etched-off high-k sidewall spacer film on the vertical walls is replaced with an ultra low-k material. ## Claims ### Claim 1 A method of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), said method comprising: on a gate structure coated with a high-k sidewall spacer film, etching off said high-k sidewall spacer film from a top surface of said gate structure and from a portion of vertical walls of said gate structure; depositing an ultra low-k material as a replacement for said etched-off high-k sidewall spacer film on said top surface and said vertical walls such that a thickness of said ultra low-k material is substantially constant on said top surface and on said vertical walls; and etching away, using a vertical etch, said ultra low-k material only on said top surface of said gate structure, thereby retaining said ultra low-k material on said vertical walls with said substantially constant thickness, wherein said gate structure controls carrier movement in an underlying channel below said gate structure and said gate structure is adjacent on each of two sides to epitaxial regions serving as source/drain functions for said MOSFET, wherein said etching off of said high-k sidewall spacer film comprises an etching of an exposed portion of said high-k sidewall spacer film followed by an over-etching of said high-k sidewall spacer film below a top surface of said epitaxial regions, thereby creating high-aspect-ratio divots adjacent to said gate structures, said high-aspect-ratio predetermined to permit a pinching off by a deposition of said ultra low-k material that will permit air spacers to form in said divots, said air spacers providing an ultra low-k value inside regions in said portion of vertical walls that are vacated by said over-etching. ### Claim 2 (depends on 1) The method of claim 1, further comprising depositing said ultra low-k material, said depositing pinching off said divots to create said air spacers. ### Claim 3 (depends on 1) The method of claim 1, wherein said etching off of said high-k sidewall spacer film comprises an etching that stops etching off said high-k sidewall spacer film at a top surface of said epitaxial regions, so that said replacing said etched-off high-k sidewall spacer film with said ultra low-k material comprises depositing said ultra low-k material on sidewalls of said gate structure above said top surface of said epitaxial regions such that said sidewalls of said gate structure are covered by a spacer film comprising a bottom portion of said high-k sidewall spacer film below said top surface of said epitaxial regions and a top portion of a layer of said ultra low-k material above said top surface of said epitaxial regions. ### Claim 4 (depends on 1) The method of claim 1, wherein said MOSFET comprises a finFET. ### Claim 5 (depends on 1) The method of claim 1, wherein said high-k sidewall spacer film comprises a SiBCN (Silicon-Boron-Carbon-Nitride) thin film. ### Claim 6 (depends on 1) The method of claim 1, wherein said ultra low-k material comprises at least one of: SiCOH, a thin film comprising silicon Si, carbon C, oxygen O, and hydrogen H; an organosilica glass (OSG); a porous xerogel; and a mesoporous silica films (MCM). ### Claim 7 (depends on 1) The method of claim 1, wherein said high-k sidewall spacer film has a k-value of approximately 5 and said ultra low-k material has a k-value no more than approximately 2. ### Claim 8 (depends on 1) A MOSFET fabricated by the method of claim 1. ### Claim 9 (depends on 2) The method of claim 2, wherein said etching off said high-k sidewall spacer film from said portion of vertical walls of said gate structure stops to retain a bottom portion of said high-k sidewall spacer film such that said sidewalls of said gate structure are covered by a spacer film comprising a bottom portion of said high-k sidewall spacer film, a middle portion of said air spacers below a top surface of said epitaxial regions, and a top portion of a layer of said ultra low-k material. ### Claim 10 A method of fabricating an semiconductor device, said method comprising: on a gate structure coated with a high-k sidewall spacer film, etching off said high-k sidewall spacer film from a portion of vertical walls of said gate structure; and depositing an ultra low-k material as a replacement for said etched-off high-k sidewall spacer film on said top surface and said vertical walls; and etching away, using a vertical etch, said ultra low-k material only on said top surface of said gate structure, thereby retaining said ultra low-k material on said vertical walls, wherein said gate structure controls carrier movement in an underlying channel below said gate structure and said gate structure is adjacent on each of two sides to epitaxial regions serving as source/drain functions for said semiconductor device, and wherein said etching off of said high-k sidewall spacer film comprises an etching of an exposed portion of said high-k sidewall spacer film followed by an over-etching of said high-k sidewall spacer film below a top surface of said epitaxial regions, thereby creating high-aspect-ratio divots between said epitaxial regions and said gate structures, said high-aspect-ratio predetermined to permit a pinching off by a deposition of said ultra low-k material that will permit air spacers to form in said divots when said ultra low-k material is deposited. ### Claim 11 (depends on 10) The method of claim 10, further comprising depositing said ultra low-k material, said depositing pinching off said divots to create said air spacers. ### Claim 12 (depends on 11) The method of claim 11, wherein said etching off said high-k sidewall spacer film from said portion of vertical walls of said gate structure stops to retain a bottom portion of said high-k sidewall spacer film such that said sidewalls of said gate structure are covered by a spacer film comprising a bottom portion of said high-k sidewall spacer film, a middle portion of said air spacers below a top surface of said epitaxial regions, and a top portion of a layer of said ultra low-k material. ### Claim 13 (depends on 10) The method of claim 10, wherein said high-k sidewall spacer film comprises a SiBCN (Silicon-Boron-Carbon-Nitride) thin film, as predetermined to have thermal characteristics to support an initial formation of said gate structure. ### Claim 14 (depends on 10) The method of claim 10, wherein said ultra low-k material comprises at least one of: SiCOH, a thin film comprising silicon Si, carbon C, oxygen O, and hydrogen H; an organosilica glass (OSG); a porous xerogel; and a mesoporous silica films (MCM).