# US 10,312,147 B2 · Multi-layer work function metal gates with similar gate thickness to achieve multi-VT for VFETs

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- Number: US 10,312,147 B2
- Document ID: US10312147B2
- Status: Granted
- Kind: B2
- Application number: 15/958,765
- Filed: 2018-04-20
- Published: 2018-10-11
- Granted: 2019-06-04
- Earliest claimed: 2017-04-06
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ruqiang Bao; Hemanth Jagannathan; Paul C. Jamison; ChoongHyun Lee
- Web page: https://patentgrep.com/patent/US10312147B2

## CPC

- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/853: {comprising FinFETs}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.

## Claims

### Claim 1

A method for forming a device having multiple field effect transistors (FETs) with each FET having a different work function gate stack, the method comprising:
forming a first FET, a second FET, a third FET, and a fourth FET over a semiconductor substrate;
forming a first work function conducting layer shared between the first, second, third, and fourth FETs;
forming a second work function conducting layer shared between the second, third, and fourth FETs;
forming a third work function conducting layer shared between the third and fourth FETs;
forming a fourth work function conducting layer over the fourth FET; and
forming at least one metal layer over the first, second, third, and fourth FETs such that a distance between the at least one metal layer and the first FET is substantially equal to a distance between the at least one metal layer and the third FET.

### Claim 2 (depends on 1)

The method of claim 1, further comprising depositing an organic planarization layer (OPL) over the at least one metal layer formed over the first, second, third, and fourth FETs.

### Claim 3 (depends on 2)

The method of claim 2, further comprising recessing the OPL such that the OPL remains between the first, second, third, and fourth FETs.

### Claim 4 (depends on 3)

The method of claim 3, further comprising recessing the at least one metal layer and the first, second, third, and fourth work function conducting layers to expose top portions of the first, second, third, and fourth FETs.

### Claim 5 (depends on 4)

The method of claim 4, further comprising stripping the OPL.

### Claim 6 (depends on 5)

The method of claim 5, further comprising forming an encapsulation layer over the first, second, third, and fourth FETs, and forming an oxide layer over the encapsulation layer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising recessing the oxide layer to form spacers adjacent the top portions of the first, second, third, and fourth FETs.

### Claim 8 (depends on 7)

The method of claim 7, further comprising stripping the remaining oxide layer and isolating the first, second, third, and fourth FETs.

### Claim 9 (depends on 8)

The method of claim 8, further comprising exposing a channel material of the first, second, third, and fourth FETs.

### Claim 10 (depends on 9)

The method of claim 9, further comprising forming source/drain regions over the channel material of the first, second, third, and fourth FETs.

### Claim 11

A method for forming a device having multiple field effect transistors (FETs) with each FET having a different work function gate stack, the method comprising:
forming a first FET, a second FET, a third FET, and a fourth FET over a semiconductor substrate;
forming a first work function conducting layer shared between the first, second, third, and fourth FETs;
forming a second work function conducting layer shared between the second, third, and fourth FETs;
forming a third work function conducting layer shared between the third and fourth FETs;
forming a fourth work function conducting layer over the fourth FET; and
forming at least one metal layer over the first, second, third, and fourth FETs such that a thickness difference between gate stacks of the first, second, third, and fourth FETs is less than about 2 nm.

### Claim 12 (depends on 11)

The method of claim 11, further comprising depositing an organic planarization layer (OPL) over the at least one metal layer formed over the first, second, third, and fourth FETs.

### Claim 13 (depends on 12)

The method of claim 12, further comprising recessing the OPL such that the OPL remains between the first, second, third, and fourth FETs.

### Claim 14 (depends on 13)

The method of claim 13, further comprising recessing the at least one metal layer and the first, second, third, and fourth work function conducting layers to expose top portions of the first, second, third, and fourth FETs.

### Claim 15 (depends on 14)

The method of claim 14, further comprising stripping the OPL.

### Claim 16 (depends on 15)

The method of claim 15, further comprising forming an encapsulation layer over the first, second, third, and fourth FETs, and forming an oxide layer over the encapsulation layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising recessing the oxide layer to form spacers adjacent the top portions of the first, second, third, and fourth FETs.

### Claim 18 (depends on 17)

The method of claim 17, further comprising stripping the remaining oxide layer and isolating the first, second, third, and fourth FETs.

### Claim 19 (depends on 18)

The method of claim 18, further comprising exposing a channel material of the first, second, third, and fourth FETs.

### Claim 20 (depends on 19)

The method of claim 19, further comprising forming source/drain regions over the channel material of the first, second, third, and fourth FETs.