# US 10,312,134 B2 · High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss

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- Number: US 10,312,134 B2
- Document ID: US10312134B2
- Status: Granted
- Kind: B2
- Application number: 14/835,093
- Filed: 2015-08-25
- Published: 2016-03-10
- Granted: 2019-06-04
- Earliest claimed: 2014-09-04
- Assignees: GlobalWafers Co., Ltd.
- Applicants: SunEdison Semiconductor Limited (UEN201334164H)
- Inventors: Qingmin Liu
- Web page: https://patentgrep.com/patent/US10312134B2

## CPC

- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10P 14/68: Organic materials, e.g. photoresists
- H10P 14/6905: {being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 90/00: Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.

## Claims

### Claim 1

A multilayer structure comprising:
a silicon wafer handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the silicon wafer handle substrate and the other of which is a back surface of the silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the silicon wafer handle substrate, and a bulk region between the front and back surfaces of the silicon wafer handle substrate, wherein the silicon wafer handle substrate has a bulk region resistivity between 2000 Ohm-cm and about 100,000 Ohm-cm;
a charge trapping layer comprising a Group IVA nitride layer, wherein the Group IVA nitride layer comprises carbon nitride;
a dielectric layer in contact with the Group IVA nitride layer, wherein the dielectric layer is selected from the group consisting of silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof; and
a semiconductor device layer in contact with the dielectric layer.

### Claim 2 (depends on 1)

The multilayer structure of claim 1 wherein the charge trapping layer comprising the Group IVA nitride layer comprises a multilayer comprising a carbon nitride layer and a silicon carbon nitride layer.

### Claim 3 (depends on 1)

The multilayer structure of claim 1 wherein the Group IVA nitride layer has an average thickness of between about 1 nanometer and about 2000 nanometers.

### Claim 4 (depends on 1)

The multilayer structure of claim 1 wherein the Group IVA nitride layer has an average thickness of between about 5 nanometers and about 2000 nanometers.

### Claim 5 (depends on 1)

The multilayer structure of claim 1 wherein the Group IVA nitride layer has an average thickness of between about 5 nanometers and about 1000 nanometers.

### Claim 6 (depends on 1)

The multilayer structure of claim 1 wherein the Group IVA nitride layer has an average thickness of between about 5 nanometers and about 500 nanometers.

### Claim 7 (depends on 1)

The multilayer structure of claim 1 wherein the Group IVA nitride layer has an average thickness of between about 200 nanometers and about 500 nanometers.

### Claim 8 (depends on 1)

The multilayer structure of claim 1 wherein the silicon wafer handle substrate comprises a wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

### Claim 9 (depends on 1)

The multilayer structure of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 2000 Ohm-cm and about 10,000 Ohm-cm.

### Claim 10 (depends on 1)

The multilayer structure of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 10,000 Ohm-cm.

### Claim 11 (depends on 1)

The multilayer structure of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 5,000 Ohm-cm.