# US 10,312,132 B2 · Forming sacrificial endpoint layer for deep STI recess

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- Number: US 10,312,132 B2
- Document ID: US10312132B2
- Status: Granted
- Kind: B2
- Application number: 15/414,752
- Filed: 2017-01-25
- Published: 2018-07-26
- Granted: 2019-06-04
- Earliest claimed: 2017-01-25
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Juntao Li; Sebastian Naczas; Peng Xu
- Web page: https://patentgrep.com/patent/US10312132B2

## CPC

- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/011: {comprising FinFETs}
- H10P 74/238: {comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a substrate, forming one or more shallow isolation trench (STI) structures defining a first region and a second region, forming a liner dielectric and forming spacers adjacent sidewalls of the plurality of fins and adjacent the one or more STI structures. The method further includes filling the one or more STI structures with an oxide layer, and incrementally recessing the oxide layer and the spacers adjacent the plurality of fins in an alternate manner until a proximal end of the second region is detected.

## Claims

### Claim 1

A method of forming a semiconductor structure, the method comprising:
forming a plurality of fins over a substrate;
forming one or more shallow isolation trench (STI) structures defining a first region and a second region;
forming a liner dielectric;
forming spacers adjacent sidewalls of the plurality of fins and adjacent the one or more STI structures;
filling the one or more STI structures with an oxide layer; and
incrementally recessing the oxide layer and the spacers adjacent the plurality of fins, multiple times, in an alternating and continuous manner, until the oxide layer is completely removed such that an entirety of each of the plurality of fins remains intact.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first region extends a length of the plurality of fins structures.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second region extends from a distal end of the plurality of fins into the substrate.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first region has a first width and the second region has a second width, the first width being greater than the second width.

### Claim 5 (depends on 1)

The method of claim 1, wherein the liner dielectric is a silicon nitride (SiN) liner.

### Claim 6 (depends on 1)

The method of claim 1, wherein the spacers are polysilicon spacers.

### Claim 7 (depends on 6)

The method of claim 6, wherein the proximal end of the second region is detected when a signal indicates low levels of the polysilicon spacers.

### Claim 8 (depends on 6)

The method of claim 6, wherein the polysilicon spacers adjacent the one or more STI structures remain intact after removal of the polysilicon spacers adjacent the plurality of fins.

### Claim 9

A method of forming a semiconductor structure, the method comprising:
forming a plurality of fins over a substrate;
forming at least one shallow isolation trench (STI) structure;
forming polysilicon spacers adjacent sidewalls of the plurality of fins and adjacent the at least one STI structure;
filling the at least one STI structure with an STI oxide; and
alternately recessing, in a continuous manner, the STI oxide and the polysilicon spacers adjacent the plurality of fins, multiple times, in a stepwise manner until the STI oxide is completely removed such that an entirety of each of the plurality of fins remains intact.

### Claim 10 (depends on 9)

The method of claim 9, wherein the at least one STI structure defines a first region and a second region.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first region extends a length of the plurality of fins structures.

### Claim 12 (depends on 11)

The method of claim 11, wherein the second region extends from a distal end of the plurality of fins into the substrate.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first region has a first width and the second region has a second width, the first width being greater than the second width.

### Claim 14 (depends on 9)

The method of claim 9, further comprising forming a liner dielectric before formation of the polysilicon spacers.

### Claim 15 (depends on 14)

The method of claim 14, wherein the liner dielectric is a silicon nitride (SiN) liner.

### Claim 16 (depends on 9)

The method of claim 9, wherein the polysilicon spacers adjacent the at least one STI structure remain intact after removal of the polysilicon spacers adjacent the plurality of fins.

### Claim 17

A semiconductor structure, comprising:
a plurality of fins formed over a substrate;
one or more shallow isolation trench (STI) structures defining a first region and a second region;
a liner dielectric;
spacers adjacent sidewalls of the plurality of fins and adjacent the one or more STI structures; and
an oxide layer for filling the one or more STI structures;
wherein the oxide layer and the spacers adjacent the plurality of fins are incrementally recessed multiple times in an alternating and continuous manner until the oxide layer is completely removed such that an entirety of each of the plurality of fins remains intact.

### Claim 18 (depends on 17)

The structure of claim 17, wherein the spacers are polysilicon spacers.

### Claim 19 (depends on 18)

The structure of claim 18, wherein the proximal end of the second region is detected when a signal indicates low levels of the polysilicon spacers.

### Claim 20 (depends on 18)

The structure of claim 18, wherein the polysilicon spacers adjacent the one or more STI structures remain intact after removal of the polysilicon spacers adjacent the plurality of fins.