# US 10,312,131 B2 · Semiconductor devices with back surface isolation

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- Number: US 10,312,131 B2
- Document ID: US10312131B2
- Status: Granted
- Kind: B2
- Application number: 15/434,611
- Filed: 2017-02-16
- Published: 2017-06-08
- Granted: 2019-06-04
- Earliest claimed: 2010-12-15
- Assignees: Efficient Power Converson Corporation
- Applicants: Efficient Power Conversion Corporation
- Inventors: Alexander Lidow; Jianjun Cao; Robert Beach; Johan T. Strydom; Alana Nakata; Guangyuan Zhao
- Web page: https://patentgrep.com/patent/US10312131B2

## CPC

- H10W 20/021: {of interconnections within wafers or substrates}
- H10D 8/70: Tunnel-effect diodes
- H10D 10/40: Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/357: {of FETs}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/01: Manufacture or treatment
- H10D 84/0158: {the components including FinFETs}
- H10D 84/05: using Group III-V technology
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/82: of only field-effect components
- H10D 86/01: Manufacture or treatment
- H10D 86/03: wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS]
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 10/30: Isolation regions comprising PN junctions
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

## Claims

### Claim 1

A method of forming an integrated device comprising a plurality of transistor devices, said method comprising:
providing a substrate, the substrate having a potential; and
forming the plurality of transistor devices on the substrate, comprising, for each of the transistor devices, the steps of:
forming a conductive well in the substrate, wherein the conductive well is electrically isolated in at least one bias polarity from the potential of the substrate;
forming at least one buffer layer over the substrate and the conductive well;
forming a device layer including a current conducting region over the at least one buffer layer;
forming a source contact and a drain contact on a top surface of the device layer and over the conductive well of the substrate;
forming a conductive via extending from the top surface of the device layer, through the device layer and the buffer layer to penetrate and terminate within the conductive well, and electrically connecting the conductive well to the source contact, such that a potential under the source contact and the drain contact is independent from the potential of the substrate, and the drain contact is independent in potential from a backside of the substrate; and
forming an isolation structure in the integrated device to isolate the conductive well of each of the transistor devices from the conductive well of neighboring transistor devices formed on the substrate, such that the potential under the source contact and the drain contact of each of the transistor devices is independent from the potential under the source contact and the drain contact of the neighboring transistor devices.

### Claim 2 (depends on 1)

The method of claim 1, wherein the isolation structure in the integrated device is formed by:
forming a photo-resist pattern definition over the device layer in a region between where the source contact and the drain contact are formed;
etching down through layers of the transistor devices in exposed areas of the photo-resist pattern at least below the conductive well;
and
filling the etched areas with an isolating material.

### Claim 3 (depends on 1)

The method of claim 1, wherein the isolation structure in the integrated device is formed by implanting isolating material into the transistor devices.

### Claim 4 (depends on 1)

The method of claim 1, wherein the isolation structure comprises an epitaxially-based substrate isolation structure by forming one or more substrate isolation layers between the substrate and the conductive well.