# US 10,312,110 B2 · Method for manufacturing an SGT-including semiconductor device

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- Number: US 10,312,110 B2
- Document ID: US10312110B2
- Status: Granted
- Kind: B2
- Application number: 15/360,488
- Filed: 2016-11-23
- Published: 2017-03-16
- Granted: 2019-06-04
- Earliest claimed: 2013-11-06
- Assignees: Unisantis Electronics Singapore Pte. Ltd.
- Applicants: Unisantis Electronics Singapore Pte. Ltd.
- Inventors: Fujio Masuoka; Nozomu Harada
- Web page: https://patentgrep.com/patent/US10312110B2

## CPC

- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/837: {comprising vertical IGFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P 32/1414: {the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon}
- H10P 32/171: {being group IV material}
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/4451: {Semiconductor materials, e.g. polysilicon}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/68: Floating-gate IGFETs
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for manufacturing a semiconductor device includes forming an SGT in a semiconductor pillar on a semiconductor substrate and forming a wiring semiconductor layer so as to contact a side surface of an impurity region present in a center portion of the semiconductor pillar or a side surface of a gate conductor layer. A first alloy layer formed in a side surface of the wiring semiconductor layer is directly connected to the impurity region and the gate conductor layer and is connected to an output wiring metal layer through a contact hole formed on an upper surface of a second alloy layer formed in an upper surface and the side surface of the wiring semiconductor layer.

## Claims

### Claim 1

A method for manufacturing an SGT-including semiconductor device, the method comprising:
a first semiconductor pillar forming step of forming a first semiconductor pillar vertically on a substrate;
a first impurity region forming step of forming a first impurity region in a lower portion of the first semiconductor pillar, the first impurity region containing a donor or acceptor impurity;
a second impurity region forming step of forming a second impurity region in the first semiconductor pillar at a position above and remote from the first impurity region, the second impurity region having the same conductivity type as the first impurity region;
a first gate insulating layer forming step of forming a first gate insulating layer so as to surround an outer periphery of the first semiconductor pillar that lies between the first impurity region and the second impurity region;
a first gate conductor layer forming step of forming a first gate conductor layer so as to surround an outer periphery of the first gate insulating layer;
a wiring semiconductor layer forming step of forming a wiring semiconductor layer in electrical contact with an outer peripheral side surface of the second impurity region, the outer peripheral side surface of the second impurity region extending vertically with respect to the substrate, wherein in the wiring semiconductor layer forming step, the wiring semiconductor layer is formed with a longitudinally extending side that horizontally extends in a plane passing through the outer peripheral side surface of the second impurity region;
a first and second alloy layers forming step of forming a first alloy layer in a side surface of the wiring semiconductor layer and forming a second alloy layer in an upper surface and the side surface of the wiring semiconductor layer so that the second alloy layer is connected to the first alloy layer and separated from the second impurity region;
a contact hole forming step of forming a contact hole on an upper surface of the second alloy layer; and
a wiring metal layer forming step of forming a wiring metal layer electrically connected to the second impurity region through the contact hole,
wherein a first SGT is formed in which when one of the first impurity region and the second impurity region serves as a source, the other serves as a drain, the first semiconductor pillar that lies between the first impurity region and the second impurity region serves as a channel, and the first gate conductor layer surrounding the outer periphery of the first gate insulating layer serves as a gate.

### Claim 2 (depends on 1)

The method for manufacturing an SGT-including semiconductor device according to claim 1, the method comprising:
a third impurity region forming step of forming a third impurity region in an upper portion of the first semiconductor pillar, the third impurity region being located above the second impurity region;
a fourth impurity region forming step of forming a fourth impurity region in the first semiconductor pillar at a position above and remote from the third impurity region, the fourth impurity region having the same conductivity type as the third impurity region;
a second gate insulating layer forming step of forming a second gate insulating layer so as to surround an outer periphery of the first semiconductor pillar that lies between the third impurity region and the fourth impurity region;
a second gate conductor layer forming step of forming a second gate conductor layer so as to surround an outer periphery of the second gate insulating layer;
the wiring semiconductor layer forming step of forming the wiring semiconductor layer in contact with the second impurity region and the third impurity region so that the wiring semiconductor layer connects the second impurity region to the third impurity region;
a fifth impurity region forming step of forming a fifth impurity region in the wiring semiconductor layer, the fifth impurity region being connected to the second impurity region, containing a donor or acceptor impurity contained in the second impurity region so as to have the same conductivity type as the second impurity region, and being in contact with the first alloy layer;
a sixth impurity region forming step of forming a sixth impurity region in the wiring semiconductor layer, the sixth impurity region being connected to the third impurity region, containing a donor or acceptor impurity contained in the third impurity region so as to have the same conductivity type as the third impurity region, and being in contact with the first alloy layer;
the second alloy layer forming step of forming the second alloy layer in the upper surface and the side surface of the wiring semiconductor layer, the second alloy layer being connected to the first alloy layer;
the contact hole forming step of forming the contact hole on the upper surface of the second alloy layer; and
the wiring metal layer forming step of forming the wiring metal layer electrically connected to the second impurity region and the third impurity region through the contact hole,
wherein a second SGT is formed in which when one of the third impurity region in contact with the second impurity region of the first SGT and the fourth impurity region serves as a source, the other serves as a drain, the first semiconductor pillar that lies between the third impurity region and the fourth impurity region serves as a channel, and the second gate conductor layer surrounding the outer periphery of the second gate insulating layer serves as a gate.

### Claim 3 (depends on 2)

The method for manufacturing an SGT-including semiconductor device according to claim 2,
wherein the wiring semiconductor layer is caused to contain a donor or acceptor impurity contained in the impurity region having the lower impurity concentration out of the second impurity region and the third impurity region;
the donor or acceptor impurity contained in the wiring semiconductor layer is thermally diffused into the first semiconductor pillar from the wiring semiconductor layer; and
the second impurity region and the third impurity region are formed in the first semiconductor pillar.

### Claim 4 (depends on 1)

The method for manufacturing an SGT-including semiconductor device according to claim 1,
wherein the contact hole is formed on the upper surface of the second alloy layer so as to contain the upper surface and the side surface of the second alloy layer in a portion of the contact hole.

### Claim 5 (depends on 4)

The method for manufacturing an SGT-including semiconductor device according to claim 4, wherein the wiring semiconductor layer is formed to have a thickness larger than a half of a length of one side of the contact hole in plan view.

### Claim 6 (depends on 2)

The method for manufacturing an SGT-including semiconductor device according to claim 2, the method comprising forming the second alloy layer so as to contact the fifth impurity region and the sixth impurity region.

### Claim 7 (depends on 2)

The method for manufacturing an SGT-including semiconductor device according to claim 2, the method comprising:
causing the wiring semiconductor layer to contain a donor or acceptor impurity;
forming a seventh impurity region in the first semiconductor pillar by thermally diffusing the donor or acceptor impurity of the wiring semiconductor layer into the first semiconductor pillar through a heat treatment; and
forming SGTs of the same conductivity type above and below the seventh impurity region.

### Claim 8 (depends on 1)

The method for manufacturing an SGT-including semiconductor device according to claim 1, wherein the wiring semiconductor layer forming step is performed such that the wiring semiconductor layer directly physically contacts the outer peripheral side surface of the second impurity region.