# US 10,312,105 B2 · Semiconductor devices using auxiliary layers for trimming margin and devices so formed

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,312,105 B2
- Document ID: US10312105B2
- Status: Granted
- Kind: B2
- Application number: 15/598,861
- Filed: 2017-05-18
- Published: 2017-09-07
- Granted: 2019-06-04
- Earliest claimed: 2015-01-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Chan-Sic Yoon; Jiung Pak; Kiseok Lee; Chan Ho Park; Hyeonok Jung
- Web page: https://patentgrep.com/patent/US10312105B2

## CPC

- H10P 50/696: {Process specially adapted to improve the resolution of the mask}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate comprising a first active pattern and a second active pattern, which are defined by a device isolation layer and are arranged spaced apart from each other in a first direction; and
a first word line extending in a second direction crossing the first direction and crossing the device isolation layer between the first and second active patterns,
wherein, when viewed in a plan view, each of the first and second active patterns is bar-shaped extending in the first direction and has a width extending in a third direction perpendicular to the first direction and crossing the second direction, and at least one of the first and second active patterns is partially overlapped with the first word line, and
wherein a distance between the first and second active patterns in the first direction is less than the width of each of the first and second active patterns.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second word line extending in the second direction and crossing the first active pattern;
a capacitor connected to the first active pattern; and
a first contact plug vertically positioned between the first active pattern and the capacitor,
wherein the first contact plug is provided on the first active pattern between the first and second word lines.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising:
a bit line extending in a fourth direction crossing the first and second directions; and
a second contact plug vertically positioned between the first active pattern and the bit line, wherein the second contact plug is provided on the first active pattern positioned at a side of the second word line and is spaced apart from the first contact plug with the second word line therebetween.

### Claim 4 (depends on 3)

The semiconductor-device of claim 3, wherein the first word line is buried in the device isolation layer between the first and second active patterns, and
wherein the second word line is buried in the first active pattern.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, further comprising a first doped region and a second doped region in the first active pattern and positioned on both sides of the second word line,
wherein the capacitor is electrically connected to the first doped region by the first contact plug, and
wherein the bit line is electrically connected to the second doped region by the second contact plug.