# US 10,312,104 B2 · Sacrificial mandrel structure with oxide pillars having different widths and resulting fins arrangements

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- Number: US 10,312,104 B2
- Document ID: US10312104B2
- Status: Granted
- Kind: B2
- Application number: 15/482,245
- Filed: 2017-04-07
- Published: 2017-09-28
- Granted: 2019-06-04
- Earliest claimed: 2016-03-22
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng
- Web page: https://patentgrep.com/patent/US10312104B2

## CPC

- H10P 50/696: {Process specially adapted to improve the resolution of the mask}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 48/30: Devices controlled by electric currents or voltages
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/22: using masks
- H10P 50/242: {of Group IV materials}
- H10P 50/287: {by chemical means}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10B 10/12: {comprising a MOSFET load element}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

## Claims

### Claim 1

An intermediate fin field effect transistor (FinFET) structure, comprising:
a semiconductor substrate;
a nitride layer directly on the semiconductor substrate;
an oxide layer directly on the nitride layer;
a sacrificial mandrel directly on the oxide layer, wherein the oxide layer is between the sacrificial mandrel and the nitride layer, and wherein the sacrificial mandrel has a width in the range of about 20 nm to about 400 nm, and wherein the sacrificial mandrel includes a sidewall portion doped with a p-type dopant;
a first oxide pillar on a first side of the sacrificial mandrel and a second oxide pillar on the opposite side of the sacrificial mandrel, wherein the first oxide pillar has a width in the range of about 10 nm to about 60 nm, and the second oxide pillar has a width in the range of about 10 nm to about 30 nm, wherein the width of the second oxide pillar is less than the width of the first oxide pillar, and the first oxide pillar is in physical contact with the doped sidewall portion of the sacrificial mandrel; and
a capping layer covering a top surface of the sacrificial mandrel including the doped sidewall portion, at least a portion of the first oxide pillar, and at least a portion of the second oxide pillar.

### Claim 2 (depends on 1)

The intermediate FinFET structure of claim 1, wherein the sacrificial mandrel is amorphous silicon, and the first oxide pillar and second oxide pillar are silicon oxide.

### Claim 3 (depends on 2)

The intermediate FinFET structure of claim 2, wherein the first oxide pillar has a width in the range of about 15 nm to about 60 nm.

### Claim 4

A plurality of semiconductor devices on a substrate, comprising:
at least ten fins on the substrate, wherein a first fin of the at least ten fins is separated from a directly adjacent second fin by a gap, G2, the second fin is separated from a directly adjacent third fin by a gap, G4, the third fin is separated from a directly adjacent fourth fin by a gap, G1, and the fourth fin is separated from a directly adjacent fifth fin by a gap, G3, wherein the gap, G1, is less than the gap, G2, and the gap, G3, is different from the gaps, G1 and G2, and gap, G4, is different from gap, G3, and each fin is separated from the directly adjacent fin by a trench, wherein gaps G2, G4, G1, and G3, form an ordered repeating sequence of gaps that is repeated at least one more time.

### Claim 5 (depends on 4)

The plurality of semiconductor devices on a substrate of claim 4, wherein a dielectric material is formed in each of the trenches.

### Claim 6 (depends on 4)

The plurality of semiconductor devices on a substrate of claim 4, further comprising, a nitride column on each of the plurality of fins.