# US 10,312,097 B2 · Salicide bottom contacts

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- Number: US 10,312,097 B2
- Document ID: US10312097B2
- Status: Granted
- Kind: B2
- Application number: 15/887,058
- Filed: 2018-02-02
- Published: 2018-08-02
- Granted: 2019-06-04
- Earliest claimed: 2017-01-27
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Praneet Adusumilli; Alexander Reznicek; Oscar van der Straten
- Web page: https://patentgrep.com/patent/US10312097B2

## CPC

- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0318: {of vertical TFTs}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a contact to a semiconductor device that includes forming a vertically orientated channel region on semiconductor material layer of a substrate; and forming a first source/drain region in the semiconductor material layer. The method may continue with forming a metal semiconductor alloy contact on the first source/drain region extending along a horizontally orientated upper surface of the first source/drain region that is substantially perpendicular to the vertically orientated channel region, wherein the metal semiconductor alloy contact extends substantially to an interface with the vertically orientated channel region. Thereafter, a gate structure is formed on the vertically orientated channel region, and a second source/drain region is formed on the vertically orientated channel region.

## Claims

### Claim 1

A vertical transistor comprising:
a vertically orientated channel region on semiconductor material layer of a substrate;
a first source/drain region in the semiconductor material layer;
a metal semiconductor alloy contact on the first source/drain region extending along a horizontally orientated upper surface of the first source/drain region, wherein the metal semiconductor alloy contact extends substantially to an interface with the vertically orientated channel region, wherein an edge of the metal semiconductor alloy contact is aligned with a sidewall of the vertically orientated channel region;
a gate structure on the vertically orientated channel region; and
a second source/drain region on the vertically orientated channel region.

### Claim 2 (depends on 1)

The vertical transistor of claim 1, wherein the vertical transistor is a p-type semiconductor device, and the metal semiconductor alloy contact is of a composition selected from the group consisting of titanium nickel silicide, titanium platinum silicide, titanium nickel germanide, titanium platinum germanide, and combinations thereof.

### Claim 3 (depends on 2)

The vertical transistor of claim 2, wherein the vertical transistor is an n-type semiconductor device, and the metal semiconductor alloy contact is comprised of nickel silicide.

### Claim 4 (depends on 3)

The vertical transistor of claim 3, wherein metal semiconductor alloy is doped with phosphorus, arsenic or a combination thereof.

### Claim 5 (depends on 2)

The vertical transistor of claim 2, wherein the metal semiconductor alloy is doped with boron, gallium or a combination thereof.

### Claim 6 (depends on 1)

The vertical transistor of claim 1, wherein the metal semiconductor alloy has a thickness ranging from about 2 nm to about 50 nm.

### Claim 7 (depends on 1)

The vertical transistor of claim 1, further comprising strapped via contacts to the metal semiconductor alloy contact.

### Claim 8

A vertical transistor comprising:
a vertically orientated channel region on semiconductor material layer of a substrate;
a metal semiconductor alloy contact on a first source/drain region extending along a horizontally orientated upper surface of the first source/drain region to an interface with the vertically orientated channel region;
an edge of the metal semiconductor alloy contact aligned with a sidewall of the vertically orientated channel region;
a gate structure on the vertically orientated channel region; and
a second source/drain region on the vertically orientated channel region.

### Claim 9 (depends on 8)

The vertical transistor of claim 8, wherein the vertical transistor is a p-type semiconductor device, and the metal semiconductor alloy contact is of a composition selected from the group consisting of titanium nickel silicide, titanium platinum silicide, titanium nickel germanide, titanium platinum germanide, and combinations thereof.

### Claim 10 (depends on 9)

The vertical transistor of claim 9, wherein the vertical transistor is an n-type semiconductor device, and the metal semiconductor alloy contact is comprised of nickel silicide.

### Claim 11 (depends on 10)

The vertical transistor of claim 10, wherein metal semiconductor alloy is doped with phosphorus, arsenic or a combination thereof.

### Claim 12 (depends on 9)

The vertical transistor of claim 9, wherein the metal semiconductor alloy is doped with boron, gallium or a combination thereof.

### Claim 13 (depends on 8)

The vertical transistor of claim 8, wherein the metal semiconductor alloy has a thickness ranging from about 2 nm to about 50 nm.

### Claim 14 (depends on 8)

The vertical transistor of claim 8, further comprising strapped via contacts to the metal semiconductor alloy contact.