# US 10,312,095 B1 · Recessed solid state apparatuses

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- Number: US 10,312,095 B1
- Document ID: US10312095B1
- Status: Granted
- Kind: B1
- Application number: 16/163,602
- Filed: 2018-10-18
- Published: 2019-05-23
- Granted: 2019-06-04
- Earliest claimed: 2017-11-21
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Dong Seup Lee; Yoshikazu Kondo; Pinghai Hao; Sameer Pendharkar
- Web page: https://patentgrep.com/patent/US10312095B1

## CPC

- H10D 64/01358: {the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/683: {being parallel to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic device, that in various embodiments includes a first semiconductor layer comprising a first group III nitride. A second semiconductor layer is located directly on the first semiconductor layer and comprises a second different group III nitride. A cap layer comprising the first group III nitride is located directly on the second semiconductor layer. A dielectric layer is located over the cap layer and directly contacts the second semiconductor layer through an opening in the cap layer.

## Claims

### Claim 1

An electronic device, comprising:
a first semiconductor layer comprising a first group III nitride;
a second semiconductor layer located directly on the first semiconductor layer and comprising a second different group III nitride;
a cap layer located directly on the second semiconductor layer, the cap layer comprising the first group III nitride; and
a dielectric layer located over the cap layer that directly contacts the second semiconductor layer through an opening in the cap layer.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the first and second layers form a heterojunction at their interface.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein the first and second semiconductor layers comprise gallium.

### Claim 4 (depends on 1)

The electronic device of claim 1, wherein the second semiconductor layer comprises aluminum.

### Claim 5 (depends on 1)

The electronic device of claim 1, further comprising an insulating layer between the dielectric layer and the second semiconductor layer, wherein the dielectric layer is located on a surface of an opening within the insulating layer.

### Claim 6 (depends on 5)

The electronic device of claim 5, wherein the insulating layer comprises a first dielectric material and the dielectric layer comprises a different second dielectric material.

### Claim 7 (depends on 1)

The electronic device of claim 1, further comprising a gate layer located over the dielectric layer within the opening.

### Claim 8 (depends on 1)

The electronic device of claim 1, wherein the cap layer and the dielectric layer have about a same thickness within the opening.

### Claim 9 (depends on 1)

The electronic device of claim 1, wherein the cap layer comprises a group V element.

### Claim 10 (depends on 1)

The electronic device of claim 1, further comprising first and second contacts having respective ohmic connections to the cap layer, wherein the opening is located between the first and second contacts.

### Claim 11

A method, comprising:
providing substrate having a first semiconductor layer comprising a first group III nitride;
forming a second semiconductor layer directly on the first semiconductor layer, the second semiconductor comprising a second different group III nitride;
forming a cap layer directly on the second semiconductor layer, the cap layer comprising the first group III nitride; and
depositing a dielectric layer over the cap layer, the dielectric layer directly contacting the second semiconductor layer through an opening in the cap layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first and second layers form a heterojunction at their interface.

### Claim 13 (depends on 11)

The method of claim 11, wherein the first and second semiconductor layers comprise gallium.

### Claim 14 (depends on 11)

The method of claim 11, wherein the second semiconductor layer comprises aluminum.

### Claim 15 (depends on 11)

The method of claim 11, further comprising forming an insulating layer such that the insulating layer is located between the dielectric layer and the second semiconductor layer, wherein the dielectric layer is located on a surface of an opening within the insulating layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the insulating layer comprises a first dielectric material and the dielectric layer comprises a different second dielectric material.

### Claim 17 (depends on 11)

The method of claim 11, further comprising forming a gate layer over the dielectric layer within the opening.

### Claim 18 (depends on 11)

The method of claim 11, wherein the cap layer and the dielectric layer have about a same thickness within the opening.

### Claim 19 (depends on 11)

The method of claim 11, wherein the cap layer comprises a group V element.

### Claim 20 (depends on 11)

The method of claim 11, further comprising forming first and second contacts having respective ohmic connections to the cap layer, wherein the opening is located between the first and second contacts.